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Archive for March 20th, 2014

RTL SOC Verification Goes Better with Synopsys VCS and Verdi

Thursday, March 20th, 2014

Real Intent will exhibit its Ascent™ and Meridian™ products for advanced SoC sign-off at the SNUG® Designer Community Expo (DCE) – part of the Synopsys® Users Group (SNUG) Silicon Valley event March 24-26 – and also will make a presentation at the first Verdi Interoperable Apps (VIA) Developers Forum there. At the DCE, Real Intent will showcase its Meridian CDC and Ascent XV working with Synopsys’ industry-leading VCS® verification solution as a part of the IC Verification community.  Real Intent’s Ascent products find elusive bugs and eliminate sources of uncertainty that are difficult to uncover using traditional Verilog or VHDL simulation, leading to both improved QoR and productivity of design teams. Meridian products accelerate sign-off verification of clock domain crossings and SDC in 500+M gate SoC designs.

At the VIA Developers Forum, myself and Mathew Yee, Sr. Application Engineer will present and highlight the features and benefits of Real Intent’s product integration with the comprehensive Verdi debug environment and its application to particular debug challenges such as clock domain crossing (CDC) verification. (more…)

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