Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
New Ascent IIV Release Delivers Enhanced Automatic Verification of FSMs
March 6th, 2014 by Graham Bell
On Feb. 26, Real Intent announced a new version of its Ascent Implied Intent Verification (IIV) tool for early functional analysis of digital designs, delivering significant enhancements for users. Ascent products find elusive bugs and eliminate sources of uncertainty that are difficult to uncover using traditional Verilog or VHDL simulation, leading to both improved QoR and productivity of design teams.
New Ascent IIV features and enhancements include:
Lisa Piper, senior manager of technical marketing at Real Intent, said, “The enhanced FSM checks and associated debug of IIV mean designers can find more bugs automatically without the need for any test benches. IIV’s root cause analysis dramatically reduces debug time by focusing the effort on the real design problems, without being distracted by related secondary issues. The enhancements we made to our SystemVerilog 2009 language support and file processing make it easier for design teams to adopt it into their existing design flows. Our Ascent products remain the fastest and highest-capacity verification solutions available for uncovering issues prior to digital simulation.”
The latest release of Ascent IIV is available immediately for download from the Real Intent web-site.
About Ascent IIV
Ascent IIV is a state-of-the-art automatic RTL verification tool. It finds bugs using an intelligent hierarchical analysis of design intent. No test bench is needed, making it easy and efficient to find RTL bugs earlier in the design flow before they become more expensive to uncover. The analysis minimizes debug time by identifying the root cause of issues, and provides the VCD traces that show the sequence of events that lead to an undesired state. Ascent IIV has the speed and capacity to handle design blocks exceeding 250K gates and provides a wide variety of complex checks including FSM deadlocks, bus issues, and constant bits and nets. If SVA or VHDL assertions written in PSL are available, Ascent IIV can use these as constraints to enhance the analysis. Please click here for a recent announcement about how Real Intent’s Ascent IIV software accelerates design debug for a customer.
Ascent and Meridian are trademarks of Real Intent, Inc.