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Archive for March, 2014

X-Verification: A Critical Analysis for a Low-Power World (Video)

Thursday, March 27th, 2014

The problem logic designers have with X’s is that RTL simulation is optimistic in behavior and this can hide real bugs in your design when you go to tapeout.  Some engineers point out that we have always had to deal with X’s and nothing has really changed.

In fact, today’s SoC employ different power management schemes that wake-up or suspend IP.  As any designer knows, when powering up logic, any X’s must be cleared on reset or within a specific short number of cycles afterword.   The situation is now much more uncertain for designers whether all possible power scenarios are considered and all X’s will be cleared correctly.

Sorting all of this out with your simulator is too much and will be too late in the design process.  So, the temptation is to supply a reset to all the flops in your design, but this will be costly in terms of precious routing density and power usage. Ideally, you would have a static tool that could analyze the rest scheme of your design and then suggest a minimum sub-set of flops that need reset lines.  This week, on March 25, Real Intent unveiled major enhancements in its  Ascent XV product for early detection and management of unknowns (X’s) in digital designs, which address this issue. (more…)

RTL SOC Verification Goes Better with Synopsys VCS and Verdi

Thursday, March 20th, 2014

Real Intent will exhibit its Ascent™ and Meridian™ products for advanced SoC sign-off at the SNUG® Designer Community Expo (DCE) – part of the Synopsys® Users Group (SNUG) Silicon Valley event March 24-26 – and also will make a presentation at the first Verdi Interoperable Apps (VIA) Developers Forum there. At the DCE, Real Intent will showcase its Meridian CDC and Ascent XV working with Synopsys’ industry-leading VCS® verification solution as a part of the IC Verification community.  Real Intent’s Ascent products find elusive bugs and eliminate sources of uncertainty that are difficult to uncover using traditional Verilog or VHDL simulation, leading to both improved QoR and productivity of design teams. Meridian products accelerate sign-off verification of clock domain crossings and SDC in 500+M gate SoC designs.

At the VIA Developers Forum, myself and Mathew Yee, Sr. Application Engineer will present and highlight the features and benefits of Real Intent’s product integration with the comprehensive Verdi debug environment and its application to particular debug challenges such as clock domain crossing (CDC) verification. (more…)

Engineers Have Spoken: Design And Verification Survey Results

Thursday, March 13th, 2014

This blog was originally published in SemiEngineering.com and I wanted to make sure EDACafe readers saw it as well.  I have also added some more content versus the original.  Enjoy!

Previously I have blogged about the verification surveys that Real Intent runs at tradeshows throughout the year.  We find it useful to track trends in tool needs and reveal what are the pain points designers are feeling.  I last reported to you, a year ago, in the blog article Clocks and Bugs, where I focused on clock-domain crossing (CDC) errors causing re-spins.

This year, I would like to add some additional highlights and trends that I see from new survey data.

(more…)

New Ascent IIV Release Delivers Enhanced Automatic Verification of FSMs

Thursday, March 6th, 2014


Chris Morrison, Chief Architect at Real Intent, speaks with Graham Bell, about the new 2014 release of the Ascent IIV automatic formal verification product. They discuss the trends in automatic formal verification, the new finite-state machine (FSM) checks in the release, what makes Ascent IIV unique in the marketplace, and lastly, customer experience with the tool. (more…)

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