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Graham Bell
Graham Bell
Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »

DVCon Panel Drill Down: “Where Does Design End and Verification Begin?” – Part 3

 
February 27th, 2014 by Graham Bell

At last year’s Design and Verification Conference (DVCon) in San Jose, Real Intent sponsored a panel on “Where Does Design End and Verification Begin?”  In this Part 3 we are continuing with the questions from the moderator and answers by the panelists.

The panel was moderated by Brian Hunter, Cavium, Inc. and panelists:

Pranav Ashar – Real Intent, Inc.
John Goodenough – ARM, Inc.
Harry Foster – Mentor Graphics Corp.
Oren Katzir – Intel Corp.
Gary Smith – Gary Smith EDA

Below are links into the video recording where the question is asked and the immediate replies and comments by the panelists.  Starting with Questions 15 the panelists shared several interesting insights about gaps with verification test-sets, and higher level modeling and had a lot of back and forth with the other members.

Q14Who has assertion synthesis?  Who can explain that to us? (Ashar, Goodenough, and Foster reply)

Q15So is there an early or later part of the design schedule where you would start applying these assertion synthesis tools? Can you start as soon as the RTL is written? (Goodenough, Ashar and Katzir reply)

Q16So the Spec is interesting since it is generally the traditional crossroads of where design and verification meet.  They start with a good quality Spec.  Do you have any recommendations for how designers can craft high quality specs because that is the earliest part where, if it is done well, makes the verification job easier.  They might be able to find bugs faster. (Goodenough, Foster, Ashar and Katzir reply)

Q17. We have had an opportunity to talk about a grab bag of tools sets that designers can now use to bring the bug validation curve in a little bit. We talked about X-properties, CDC,  of course Lint, and now assertion synthesis, and providing good documention.  Are there any coming future technologies that are going to add to that? (Katzir, Smith, Foster and Ashar reply)

Q18We have spent a lot of time talking about how designers can contribute more.  What about the other direction?  What about verification techniques applied to the architectural process? We have at our disposal a simulation vehicle capable of operating at the transaction level with constraints and a knowledge of timing. Is there anyone applying testbench skills to validate what the architecture is going to look like? (Goodenough, Ashar, Smith and Katzir reply)

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