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Graham Bell
Graham Bell
Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »

DVCon Panel Drill Down: “Where Does Design End and Verification Begin?” – Part 2

February 20th, 2014 by Graham Bell

At last years Design and Verification Conference (DVCon) in San Jose, Real Intent sponsored a panel on “Where Does Design End and Verification Begin?”  In this Part 2 we are continuing with the questions from the moderator and answers by the panelists.

The panel was moderated by Brian Hunter, Cavium, Inc. and panelists:

Pranav Ashar – Real Intent, Inc.
John Goodenough – ARM, Inc.
Harry Foster – Mentor Graphics Corp.
Oren Katzir – Intel Corp.
Gary Smith – Gary Smith EDA

Below are links into the video recording where the question is asked and the immediate replies and comments by the panelists.  The end-user insights by Goodenough from ARM and Katzir from Intel are particularly interesting.

Q9. (Brian Hunter speaking) I wanted to talk about something that Oren Katzir said earlier. At Intel, Oren, you have Verification IP that is coming from within the company and from external vendors. Is it true that you have your designers actually doing the verification by consuming this IP? (Katzir replies)

Q10. Would you say verification engineers are often skilled at breaking a design? Finding out how to break a design by not knowing how it works internally? (Katzir replies)

Q11. For companies like mine (Cavium), where we develop IP in-house, the design themselves actually mature along with the environment.  Trying to provide a formal analysis early on in the  project, as Dr. Goodenough was saying, proves the whole design is incomplete.  There is a point in time where you want to run these formal checks.  Too early and you are proving its incomplete, too late and you are then finding bugs that are more expensive.  Is there a particular point in time that you think applying these techniques is worthwhile? (Goodenough, Foster and Ashar reply)

Q12. So, we are asking our designers now to not only do design, and the synthesis and the timing, we also want them to do the lint, which they have historically been responsible for, we want them to analyze the code coverage, we want them to do CDC, and X (verification) and static methods. Are there any others needed for debug? (Smith, Goodenough and Katzir reply)

Q13. I think we are asking a lot of our designers aren’t we?  We asking them to have a very varied set of skills at this point.  They often tend to think in terms of RTL, and in terms of timing.  We are asking them to take on more knowledge of the software space.  We started this with assertions years ago and that is a skill set unto itself.   For example, when we run a simulation that fails the verification engineer usually finds a problem in the environment.  Are we first  asking the designer to triage that and try to take that into the environment? Where do we start? (Goodenough, Foster, Smith and Ashar reply)

Next week we present part 3.

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