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Graham Bell
Graham Bell
Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »

DVCon Panel Drill Down: “Where Does Design End and Verification Begin?” – Part 1

February 13th, 2014 by Graham Bell

At last years Design and Verification Conference (DVCon) in San Jose, Real Intent sponsored a panel on “Where Does Design End and Verification Begin?”

The panel was moderated by Brian Hunter, Cavium, Inc. and panelists:

Pranav Ashar – Real Intent, Inc.
John Goodenough – ARM, Inc.
Harry Foster – Mentor Graphics Corp.
Oren Katzir – Intel Corp.
Gary Smith – Gary Smith EDA

Brian opened the panel with the following remarks and then asked a series of questions.  Below are links into the video recording where the question is asked and the immediate replies and comments by the panelists.  If you don’t have time to listen for the full 20 minutes, jump down to Questions 6, 7 and 8 to see the highlights for part 1.  Next week we present part 2.

(Brian Hunter begins) Our topic today is the blurring lines between design and verification. Most people know that verification schedules are the long pole and getting too long and we need designers to take on a larger role in the verification process.

Q1. Let me start with  you Dr. Ashar. What are we talking about today? Are we saying designers need to start doing the verification and exiting the era of specialization?

Q2. In what ways are we saying designers need to contribute more to the verification process?

Q3. So early tools like Lint are ones that designers run. Can designers do a number of things?

Q4. So the CDC and X-verification tools that you are talking about, some of these static analysis tools, are they getting to the point where they are part of a ‘push-button’ operation in the way that lint has become? Can you answer that Mr. Foster?

Q5. Are we seeing increasing adoption rates of these techniques? We know that formal analysis is a complex set of tools that require hand-holding. I feel it has over-promised and under-delivered for the last number of years. Do you agree Mr. Smith?

Q6. At Cavium, we sell our chips into a very broad marketplace.  And as such, our SOC designs have to be highly configurable, so we have found that formal tools are encumbrance for us.  What is the sweet spot for formal analysis?  Where does it really shine?  (Dr Ashar replies)

Q7. So we are tricking some of the designers and verification engineers to using formal techniques without making it as difficult as it used to be? (Dr. Ashar, Mr. Foster and Mr. Katzir reply)

Q8. Dr. Goodenough, You guys have used formal analysis at ARM. Is that correct? (Dr. Goodenouch shares his experience)

What are your thoughts on the line between design and verification?

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