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Archive for January 30th, 2014

Progressive Static Verification Leads to Earlier and Faster Timing Sign-off

Thursday, January 30th, 2014

I originally wrote and posted this blog here on  It is reproduced below.

January 22, 2014 — As SOC design crosses the billion-gate threshold the cost of errors grows dramatically. The demand that engineers ensure their work is as correct as possible — and as soon as possible — in the design process has become more insistent. Letting errors slip forward one stage closer to implementation means their impact will grow while their causes become obscured and success is delayed. The design sign-off process itself has grown more complex, and the register-transfer level (RTL) is now where sign-off begins.

A starting point for the sign-off regimen is verification of the timing behavior of the heterogeneous IP used in an SOC and how the IP interfaces with the host design, including how clocks and signals cross any interfaces. Clocking schemes must be defined to enable earlier static analysis before it reaches the simulation stage. However, before timing analysis and simulation begin, designs must be cleaned using Lint tools.

Modern Lint tools have evolved to the point where they can handle full-chip designs and yet still offer concise hierarchical reporting. The availability of low-noise reporting means less time waiving violations and more time cleaning easy-to-fix issues. Because of the lower-noise, designers can use the tool earlier and more often. However, an RTL Lint tool requires only rule-setup and, therefore, cannot provide a deep analysis.


Verific’s Front-end Technology Leads to Success and a Giraffe!

Thursday, January 30th, 2014


Qun Li, Senior Staff Engineer at Real Intent with Michiel Ligthart, President and COO of Verific

Just this week, Michiel Ligthart from Verific dropped by for a visit.  Real Intent has enjoyed a long-term winning collaboration with their team and have used Verific’s leading HDL front-end for many years. They continue to keep us up to date with the latest developments in the SystemVerilog language.

Michiel brought a gift for one of our software developers, Qun Li, who has been supporting the integration of Verific software into our verification suite.  He surprised her with the Verific mascot: a huge stuffed giraffe!

A special thanks to Michiel for honoring Qun and we look forward to more success in the years ahead.





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