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Archive for January 23rd, 2014

CDC Verification of Fast-to-Slow Clocks – Part Three: Metastability Aware Simulation

Thursday, January 23rd, 2014

In Parts One and Two, we discussed the use of structural and formal checks when there is a fast-to-slow transition in a clock domain crossing. In this blog, we will present the third and final step using a design’s testbench.

The next step in the verification process of fast-to-slow clock domain crossings is to do metastability-aware simulation on the whole design.  When running a regular simulation test bench, there is no concept of what could happen to the design if there was metastability present in the data or control paths within the design.  One of the key reasons for doing CDC checks is to ensure that metastability does not affect a design.  After structural analysis ensures that all crossings do contain synchronizers, and formal analysis ensures that the pulse width and data are stable, a whole-chip metastability-aware simulation is needed to see if the design is still sensitive to metastability. Functional monitors and metastability checkers are shown in Figure 7.  No changes are made to the design, and the necessary monitors and checkers are written in an auxiliary Verilog simulation test bench file. This auxiliary file is simply referred to by the original simulation test bench file to invoke the metastability checking.  As a prerequisite, this step requires that the design have a detailed simulation test bench.

Figure 7 – Metastability aware simulation checks the tolerance of downstream logic to the presence of jitter in the data path through the use of functional monitors and CDC checkers.

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