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Dr. Roger B. Hughes, Director of Strategic Accounts
Dr. Roger B. Hughes, Director of Strategic Accounts
Dr. Roger B. Hughes is a renowned international expert in formal verification technologies and has over 20 years experience in the EDA industry working both at start-up companies in lead engineering roles and publicly traded companies in managing and directing technical product development. He … More »

CDC Verification of Fast-to-Slow Clocks – Part One: Structural Checks

January 9th, 2014 by Dr. Roger B. Hughes, Director of Strategic Accounts

This is the first in a short blog series that addresses the issue of doing clock domain crossing analysis where the clocks differ in frequency, and the use of three different techniques for a complete analysis.


CDC checking of any asynchronous clock domain crossing requires that the data path and the control path be identified and that the receive clock domain data flow is controlled by a multiplexer with a select line that is fed by a correctly synchronized control line.  Meridian CDC will always identify all the data and associated control paths in a design and will ensure that the control signals passing from a transmit clock domain to an asynchronous receive clock domain are correctly synchronized.  There are three separate techniques that are used within Meridian CDC: structural checking, formal checks and simulation-based injected metastability checks.


The structural checking approach does not care if the asynchronous transitions are slow to fast clocks or fast-to-slow clocks.  It will ensure that all the transitions are correctly synchronized in terms of having the appropriate synchronizer flops.  From a structural perspective, the entire design can be checked in one run and all the clock domain transitions checked for correctness.  Let’s look at an example CDC in Figure 1, with transmit clock Clk1 on the left (orange flops), and the receiving clock Clk2 on the right (blue flops).

Fig. 1 – A Typical Synchronized Control and Data Clock Domain Crossing.

It can be seen in Figure 2, where positive going clock edges are shown by the vertical lines, that all will work well for a slow-to-fast clock transition.  This is because any change of a control signal in the slow domain will always be captured by one of the edges of the receive domain clock, Clk2, before Clk1 causes the control signal to be released since Clk2 is faster than the transmit domain clock, Clk1.  Also, for slow-to-fast clock transitions the data will typically always be stable long enough to be captured and transmitted through to the receive domain.  In Figure 2, the possible Clk2 edges that could capture the TX CNTL signal in RX CNTL Sync2 flop are shown with dashed vertical lines.

Figure 2 – Slow-to-Fast Clock Crossing. There are many possible clock edges, shown dashed, of RX Clk2 that can sample the value held in the TX CNTL flop. The dot-dash edge is the first possible transition into Sync1, dashed are transitions into Sync2. There is no issue with TX CNTL period as long as the signal is sampled by one clock edge of TX Clk1.

However, the situation is different in a fast-to-slow clock domain crossing.  When there is a fast-to-slow transition, there is a possibility that a short duration control pulse may be completely missed by the receive domain.  To address this concern, and others that cannot be addressed by a purely structural CDC check, formal analysis is required.

Next time we will look at how formal analysis can verify this kind of transition.

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