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Archive for January, 2014

Progressive Static Verification Leads to Earlier and Faster Timing Sign-off

Thursday, January 30th, 2014

I originally wrote and posted this blog here on  It is reproduced below.

January 22, 2014 — As SOC design crosses the billion-gate threshold the cost of errors grows dramatically. The demand that engineers ensure their work is as correct as possible — and as soon as possible — in the design process has become more insistent. Letting errors slip forward one stage closer to implementation means their impact will grow while their causes become obscured and success is delayed. The design sign-off process itself has grown more complex, and the register-transfer level (RTL) is now where sign-off begins.

A starting point for the sign-off regimen is verification of the timing behavior of the heterogeneous IP used in an SOC and how the IP interfaces with the host design, including how clocks and signals cross any interfaces. Clocking schemes must be defined to enable earlier static analysis before it reaches the simulation stage. However, before timing analysis and simulation begin, designs must be cleaned using Lint tools.

Modern Lint tools have evolved to the point where they can handle full-chip designs and yet still offer concise hierarchical reporting. The availability of low-noise reporting means less time waiving violations and more time cleaning easy-to-fix issues. Because of the lower-noise, designers can use the tool earlier and more often. However, an RTL Lint tool requires only rule-setup and, therefore, cannot provide a deep analysis.


Verific’s Front-end Technology Leads to Success and a Giraffe!

Thursday, January 30th, 2014


Qun Li, Senior Staff Engineer at Real Intent with Michiel Ligthart, President and COO of Verific

Just this week, Michiel Ligthart from Verific dropped by for a visit.  Real Intent has enjoyed a long-term winning collaboration with their team and have used Verific’s leading HDL front-end for many years. They continue to keep us up to date with the latest developments in the SystemVerilog language.

Michiel brought a gift for one of our software developers, Qun Li, who has been supporting the integration of Verific software into our verification suite.  He surprised her with the Verific mascot: a huge stuffed giraffe!

A special thanks to Michiel for honoring Qun and we look forward to more success in the years ahead.





CDC Verification of Fast-to-Slow Clocks – Part Three: Metastability Aware Simulation

Thursday, January 23rd, 2014

In Parts One and Two, we discussed the use of structural and formal checks when there is a fast-to-slow transition in a clock domain crossing. In this blog, we will present the third and final step using a design’s testbench.

The next step in the verification process of fast-to-slow clock domain crossings is to do metastability-aware simulation on the whole design.  When running a regular simulation test bench, there is no concept of what could happen to the design if there was metastability present in the data or control paths within the design.  One of the key reasons for doing CDC checks is to ensure that metastability does not affect a design.  After structural analysis ensures that all crossings do contain synchronizers, and formal analysis ensures that the pulse width and data are stable, a whole-chip metastability-aware simulation is needed to see if the design is still sensitive to metastability. Functional monitors and metastability checkers are shown in Figure 7.  No changes are made to the design, and the necessary monitors and checkers are written in an auxiliary Verilog simulation test bench file. This auxiliary file is simply referred to by the original simulation test bench file to invoke the metastability checking.  As a prerequisite, this step requires that the design have a detailed simulation test bench.

Figure 7 – Metastability aware simulation checks the tolerance of downstream logic to the presence of jitter in the data path through the use of functional monitors and CDC checkers.


CDC Verification of Fast-to-Slow Clocks – Part Two: Formal Checks

Thursday, January 16th, 2014

In Part One, we ended the discussion noting that when there is a fast-to-slow transition, there is a possibility that a short duration control pulse may be completely missed by the receive domain and a formal analysis is required to discover if this is a potential problem. We will look at how formal analysis can verify this kind of transition.

A formal check also is required on a slow-to-fast data crossing with feedback.  In such a circuit, as shown in Figure 4, an acknowledge signal coming from the receiving fast-clock domain to the transmitting slow-clock domain also requires a formal Pulse Width check.  Although the control pulse (request) is going from slow to fast and does not need a formal pulse width check, the acknowledge pulse-width check is necessary because the acknowledge signal (the feedback circuit) is going from a fast to a slow clock and, in order for the acknowledge to be properly captured, the acknowledge pulse (transmitted from the receiving side) must be sufficiently wide to be captured (received on the transmitting side) by the slower clock domain of the transmitting side flops. Failure to check for this condition is the reason behind many a request/acknowledge circuit not working as expected. Note that feedback circuits in a fast-to-slow crossing are operating in a slow-to-fast mode and the acknowledge signal in such a circuit does not need to be pulse-width checked. In short, all fast-to-slow control signal transitions, whether connected in a feed-forward or a feedback manner need to be formally pulse-width checked to ensure integrity of the control aspect of the clock domain crossing.

Figure 4 – Slow-to-Fast Clock Crossing with Feedback (red flops are slow clock, blue flops are fast clock).


CDC Verification of Fast-to-Slow Clocks – Part One: Structural Checks

Thursday, January 9th, 2014

This is the first in a short blog series that addresses the issue of doing clock domain crossing analysis where the clocks differ in frequency, and the use of three different techniques for a complete analysis.


CDC checking of any asynchronous clock domain crossing requires that the data path and the control path be identified and that the receive clock domain data flow is controlled by a multiplexer with a select line that is fed by a correctly synchronized control line.  Meridian CDC will always identify all the data and associated control paths in a design and will ensure that the control signals passing from a transmit clock domain to an asynchronous receive clock domain are correctly synchronized.  There are three separate techniques that are used within Meridian CDC: structural checking, formal checks and simulation-based injected metastability checks.


2013 Highlights And Giga-scale Predictions For 2014

Thursday, January 2nd, 2014

There were 5 key developments that stood out for me in 2013 and I have 4 predictions for 2014 I think would of interest to the EDACafe audience.

2013 Highlights

  1.  We are now in the world of 8-core processors. Both the new Xbox One and the Sony PS4 gaming systems employ big 8-core AMD CPUs. And MediaTek has announced the MT6592, the first cell-phone chip that uses 8 ARM A-7 processors running simultaneously at 2GHz. I know, I know, you are asking yourself “do I really need 8-core functionality in my pocket?” Probably not this week, but soon you will wonder, “How did I live without it?”
  2. The 50th anniversary of Design Automation Industry was celebrated this year with a gala event in Silicon Valley to raise money for the EDA Oral History Project. The EDA Consortium’s “Back to the Future Event” had more than 250 in attendance and had a wonderful vibe. There was even a psychedelic time tunnel. Everyone I spoke to afterwards told me what a good time they had. Kudos go out to Kathyrn Kranen, Chair of EDAC, and to Bob Gardner and Jennifer Cermak, staff members who put it all together with a host of sponsors including Jill Jacobs from MOD Marketing. The industry is really founded and runs on the genius and talent of so many people. Click on the link to find out more: (more…)
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