Open side-bar Menu
 Real Talk

Archive for 2014

Seasons Greetings from Real Intent!

Thursday, December 18th, 2014

May you enjoy health, happiness, and peace in this holiday season and through the coming year!

From the staff at (more…)

Best of “Real Talk”, Q4 Summary and Latest Videos

Thursday, December 11th, 2014

Real Intent has had an exciting 2014!  In the last few months we have announced a new release of Meridian CDC , new distribution partners in Taiwan and India, and seen many of you at trade shows in Silicon Valley, China, Israel, Japan, Germany and the United Kingdom.  Our YouTube video channel keeps you up to date on all the latest developments at Real Intent, with our most recent on the New 2014 Release of Meridian CDC Meets Challenge of Billion-gate SoCs.  I also discussed “Beer, New Meridian CDC, and Arnold Schwarzenegger?! ” with Sean O’kane of ChipEstimate in an ARM TechCon video interview.

There have been over 50 postings on the Real Talk blog this year, and I have selected the most popular ones read by the EDACafe audience. Here are the top five:

Redefining Chip Complexity in the SoC Era
CDC Verification of Fast-to-Slow Clocks (a three part series)
Fundamentals of Clock Domain Crossing Verification: (a four part series)
Ascent Lint Rule of the Month: ARITH_CONTEXT
Engineers Have Spoken: Design And Verification Survey Results

As you can see clock-domain crossing (CDC) remains a very hot topic. Look for more postings on this sign-off requirement in the coming year.

Happy Holidays!

P2415 – New IEEE Power Standard for Unified Hardware Abstraction

Thursday, December 4th, 2014

The IEEE announced in September that is was launching working a on a new power standard called P2415. This blog gives the background for this new effort.

The current low power design and verification standard (IEEE 1801-2013 and IEEE P1801) is focused on the voltage distribution structure in design at Register Transfer Level (RTL) description and below. It has minimal abstraction for time (having only an interval function for modeling clock frequency), but depends on other hardware oriented standards to abstract events, scenarios, clock trees, etc. which are required for energy proportional design, verification, modeling and management of electronic systems. The necessary abstractions of hardware, as well as layers and interfaces in software are not yet defined by any existing standards. (more…)

The Evolution of RTL Lint

Thursday, November 27th, 2014

This article was originally published on TechDesignForums and is reproduced here by permission.

It’s tempting to see lint in the simplest terms: ‘I run these tools to check that my RTL code is good. The tool checks my code against accumulated knowledge, best practices and other fundamental metrics. Then I move on to more detailed analysis.’

It’s an inherent advantage of automation that it allows us to see and define processes in such a straightforward way. It offers control over the complexity of the design flow. We divide and conquer. We know what we are doing.

Yet linting has evolved and continues to do so. It covers more than just code checking. We begun with verifying the ‘how’ of the RTL but we have moved on into the ‘what’ and ‘why’. We use linting today to identify and confirm the intent of the design.

A lint tool, like our own Ascent Lint, is today one of the components of early stage functional verification rather than a precursor to it, as was once the case.

At Real Intent, we have developed this three-stage process for verifying RTL: (more…)

Parallelism in EDA Software – Blessing or a Curse?

Thursday, November 20th, 2014

To satisfy demands for lower-power and higher performance, the use of multiple CPU cores is a norm in SoC design.  The interaction of multiple cores and the surrounding semiconductor IP, presents new challenges to verification.  But what about EDA tool providers?  How can the use of multple CPUs improve performance and throughput in their tools?  What software caveats do they need to be aware to support processing by parallel CPUs?  Pranav Ashar, CTO at Real Intent gives his perspective below.

home1[1]

EDA tools must be exploit parallelism to keep up with SoC complexity, or we will be attempting to designing next-generation chips on what effectively will be antique hardware.

A couple of factors have combined to reduce the pace at which parallelism has been adopted in EDA tools. It is common to overlook the latency impact when designing parallel programs that communicate with physical memory.  Cache-coherency and memory access latency are often encountered examples that lowers the processing throughput of a tool on a multi-core processor.  Fine-grain multi-threading in EDA tools quickly triggers some of these latency bottlenecks – for the typical SoC benchmark, these limits are reached rather rapidly.

(more…)

How Big is WWD – the Wide World of Design?

Thursday, November 13th, 2014

Its a fact of life that semiconductor design is a world-wide activity, and that EDA companies are helping customers in a 24 hour day. How international is this world? According to the latest statistics from the EDA Consortium, over 50% of the business activity is outside North America.  The total of EDA, semiconductor IP and design services revenue was 6.9 billion dollars in 2013.  Comparing this to a world population of 7.1 billion means roughly one dollar per person was spent on the wide world of design.

EDA and SIP distribution

Fig. 1. Distribution of World-Wide EDA, IP and Services Revenue (EDA Consortium)

(more…)

CMOS Pioneer Remembered: John Haslet Hall

Thursday, November 6th, 2014

I still get the daily newspaper delivered to my house, the San Jose Mercury News.   I came across the obituary for John Haslet Hall, one of the leading innovators at the birth of CMOS technology in Silicon Valley.  I had not heard of Hall, and thought that you might also want to learn of his many wide-ranging contributions to the world of semiconductors.


John Haslet HallJohn Haslet Hall, son of the late William McLaurine Hall, Jr and Mary Helen (Ent) Hall, was born July 11, 1932 and died October 30, 2014.

Hall was an early and prolific Silicon Valley inventor. In a career that spanned over 60 years, Hall developed technology included in over 20 fundamental patents, including pioneering work in low-power CMOS integrated circuit technology. A 1992 San Francisco Chronicle article referred to Hall as, “one of Silicon Valley’s unsung innovators.”
Hall served in the U.S. Navy in the late 1950s, working with aircraft electronics development and testing, often riding in planes that were pulling target drones to collect data. He graduated from the University of Cincinnati in 1961 and sought to apply his chemical engineering education in the nascent semiconductor industry.

(more…)

Is Platform-on-Chip The Next Frontier For IC Integration?

Thursday, October 30th, 2014

I was musing the other day about the completeness of SoCs – they include a mix of embedded processors for programmable functionality, hardware engines that accelerate specific features such as graphics, and multiple interfaces for memory, buses, and peripherals. And this remarkably complete solution is delivered on a single die. We have the perfect building block for creating systems with high-value and low-cost. But, even with Moore’s law allowing us to build more complex silicon, is new feature integration a scalable future for SoCs?

My conclusion is that we are approaching a steady state. From what I see, SoC design is still a custom solution in many ways, tailored to fit a generation of parts that meet some specific requirements. While complete in itself, the features cast in silicon offer only a coarse control of functionality. This leaves the end-user having to provide additional software and hardware to fill in any feature gaps at additional cost and time spent. While the intended and configured functions of the SoC might been implemented, any feature extensions may have compromises in performance.

(more…)

DVClub Shanghai: Making Verification Debug More Efficient

Thursday, October 23rd, 2014

DVClub Shanghai took place on Sept. 26, 2014 with presentations by Real Intent, Solvertec, Mentor Graphics, Cadence, Synopsys and ARM.  The theme of the meeting was “Making Verification Debug More Efficient.”   Before I talk about two of the presentations that were recorded, here is some quick background on DVClub Shanghai which started at the end of 2013.

It was initiated by

The principle goal of DVClub is to have fun while helping build the verification community through quarterly educational and networking events. The DVClub events are targeted to the semiconductor industry in China, with a focus on design verification. Membership is free and is open to all non-service provider semiconductor professionals.  Most members work in verification, but there are also plenty of entrepreneurs, students, managers, investors, and even design engineers who attend. There are at least 4 events every year: March, June, September and December.

Presentations

Mike Bartley opened the event with a talk that was titled “Improving Debug – Our biggest Challenge?”   If you follow the link you can see the recording of his presentation, where he talks about the 6 things that we need for improved debug.

My presentation was on “Shortening Debug with New Methods in Static Verification.(more…)

ARM TechCon Video: Beer, New Meridian CDC, and Arnold Schwarzenegger ?!

Thursday, October 16th, 2014

At ARM Tech Con 2014, I discussed beer, the new release of our Real Intent clock-domain crossing software Meridian CDC, and a new spokesperson for our company, with Sean O’Kane of ChipEstimate.TV.  Enjoy!

CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy