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Graham Bell
Graham Bell
Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »

Semi Design Technology & System Drivers Roadmap: Concluding Thoughts

December 19th, 2013 by Graham Bell

Andrew B. Kahng, Professor of CSE and ECE, Univ. of California at San Diego presented a paper on “The ITRS Design Technology and System Drivers Roadmap: Process and Status” at the 50th Design Automation Conference in Austin, TX.   This important review of the technology challenges that are in front of the EDA industry and what is the current status is presented here below in this final posting of a blog series.


The Design Chapter in the ITRS has for well over a decade defined technology requirements and design challenges for the EDA industry and the VLSI CAD research community. Design technology roadmaps for DFM, low-power design, 3D/TSV integration, More Than Moore, etc. are continually added to maintain relevance of the roadmap. Recent Design Cost and Low-Power Design models highlight the challenges of design productivity, software design cost, and power management in future SOC and MPU designs. At the same time, the System Drivers Chapter has provided models for key market drivers as well as basic chip parameters (layout density, clock frequency, power dissipation, etc.) that bind the ITRS together via the Overall Roadmap Technology Characteristics. The MPU driver model has evolved frequency and power attributes in response to disappearing microarchitectural knobs, emergence of power limits, and challenges of device leakage; further changes (adding uncore elements, evolution of MPU-PCC for micro-server, updated die area modeling) are likely in the near future. The past decade has also seen increased reliance on “design-based equivalent scaling” (e.g., methods for activity factor reduction without compromising throughput or performance) to continue the semiconductor value proposition, and rapidly growing involvement in cross-TWG issues ranging from variability limits to device requirements.

The future of design technology roadmapping, and of the Design TWG’s work in the ITRS, will be affected by a variety of technical, business and cultural factors.

  • Past foundations of the ITRS seem increasingly shaky. For example, A-factors may no longer be constant across multiple technology nodes. Mx and poly pitches (i.e., horizontal vs. vertical densities) may scale at different rates. The fundamental assumption of 2× density scaling per node may be already long past; whether the industry can flourish with, e.g., 1.4× density scaling per node is an open question.
  • Tremendous uncertainty with respect to patterning technology (e.g., timing of EUV, directed self-assembly), cost models (e.g., triple- and quadruple-patterning), device and interconnect structures and properties (tunnel FETs, resistive RAMs, drive vs. leakage currents), and high-value applications all present challenges to the roadmapping of design technology requirements.
  • Fewer resources are available for ITRS activity even as the scope of the roadmap widens (MEMS, More Than Moore, new storage and switch elements, 3D integration) and the difficulty of the roadmapping task increases. Greater automation is needed to check consistency and impacts of proposed roadmap changes, a la the “Living ITRS” efforts of a decade ago [4].
  • An oligopolistic EDA industry, along with continued consolidation and disaggregation in the semiconductor industry, as well as unwillingness to share competitive (as opposed to pre-competitive) data, (see footnote 1) means that leading companies more frequently “opt out” of roadmap participation. There is a risk of a “vicious cycle” of decreased roadmap participation and decreased roadmap value.
  • Communication across supplier industries, across the design manufacturing interface, and across academia-industry boundaries is increasingly needed to optimize technology investments and maximize the returns from the roadmapping process. As the industry faces an explosion of post-CMOS, postoptical technology options, it seems appropriate to at least revisit the concept of “shared red bricks”.

Against this backdrop, there is some good news: Members of the design, EDA and research communities are willing to find common cause in the design technology roadmap. At the 2009 and 2010 EDA Roadmap Workshops [19], representatives from leading EDA companies, semiconductor companies, and research consortia commenced a dialogue to analyze needs and status of EDA roadmapping. See footnote 2. Other discussions sought new mechanisms by which more of the community could contribute to the design technology roadmap. And the really good news for EDA and VLSI CAD: If anything remains essential to the future of Moore’s Law scaling, it will be design technology, and design-based equivlent scaling.


Dr. Juan-Antonio Carballo has co-chaired the U.S. and International Design TWGs with me for the past decade, and has been particularly influential in the conception of the System Drivers Chapter as well as iNEMI and More Than Moore interactions. Dr. Kwangok Jeong developed and maintained the MPU, power, frequency and A-factor models during the critical years of 2007-2011, which saw many Design-PIDS interactions regarding roadmap for device power vs. performance. This paper would not exist without the help of UCSD Ph.D. students Tuck-Boon Chan, Siddhartha Nath, Wei-Ting Jonas Chan, and Ilgweon Kang. Many participants in the ITRS Design and System Drivers efforts, and in the overall ITRS effort, have contributed valuable insights and perspectives over the years. I also thank Dr. Sani Nassif (who has for years driven the DFM section of the Design Chapter) for organizing the special session which led to the writing of this paper.


  1. It is suboptimal for students at UCSD to “predict” designs and cell libraries that industry has already developed, or for students at Purdue to develop ab initio models for device structures that again have already been developed. Yet, these are the mechanisms by which core material and data is generated in the ITRS today.
  2. The 2009 workshop addressed such questions as “What would make an EDA roadmap more useful?”, “Which EDA areas lack most in roadmap efforts?”, and “Which EDA areas are behind what the roadmaps say?” The 2010 workshop then identified gaps in the EDA roadmap (system-level executable specification, designspace exploration and pathfinding, EDA scaling requirements in light of evolving computing platforms, power-driven design, and design for resilience), reached agreement on the nature of EDA, and identified challenges in filling in the EDA roadmap gaps (incremental design flows, new design for cost methodologies, and an expanded scope of EDA moving to system-level design).


[4] A. E. Caldwell, Y. Cao, A. B. Kahng, F. Koushanfar, H. Lu, I. L. Markov, M. R. Oliver, D. Stroobandt and D. Sylvester, “GTX: The MARCO GSRC Technology Exploration System”, Proc. DAC, 2000, pp. 693-698.

[19] EDA Roadmap Workshop at DAC 2010.

Copyright Notice

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. DAC’13, May 29 – June 07 2013, Austin, TX, USA. Copyright 2013 ACM 978-1-4503-2071-9/13/05 …$15.00.

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