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Archive for November 28th, 2013

Customer Reports Results of Smarter RTL Verification

Thursday, November 28th, 2013

I originally wrote and posted this blog here on SemiEngineering.com.  It is reproduced below.

SoC verification is gearing up for renewed competition among the big vendors and verification-only companies like Real Intent. They are delivering their next-generation SoC verification suites with a focus on specific areas of concern. Clock-domain crossing, X-verification and reset optimization, SDC correctness and consistency, are some of the areas that are receiving dedicated RTL analysis using static analysis. Static analysis is a mix of structural and formal techniques that let designers focus on verification and not on customizing the tool to attack a problem area.

Besides raw speed, and capacity, the newest tools are addressing the data management for sign-off of these SoCs. Smart reporting and assisted debug is a key requirement otherwise designers and verification teams will drown in a flood of analysis results. All of this innovation and targeted investment will be making SoC sign-off manageable, if not easier.

Recently, I saw the importance of having smart debug reporting in the results of an evaluation of Real Intent’s Ascent IIV tool by a customer in Japan. (more…)

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