The propagation of unknown (X) states has become a more pressing issue with the move toward billion-gate SoC designs. The sheer complexity and the common use of complex power management schemes increase the likelihood of an unknown ‘X’ state in the design translating into a functional bug in the final chip.
This article describes a methodology that enables design and verification engineers to focus on the X states that represent a real risk, and to set aside those which are artifacts of the design process.
The idea is to reduce project time, particularly that spent in simulation, and overcome the limitations inherent in high-level techniques at both RTL and gate level. (more…)