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Archive for October, 2013

Minimizing X-issues in Both Design and Verification

Thursday, October 31st, 2013

The propagation of unknown (X) states has become a more pressing issue with the move toward billion-gate SoC designs. The sheer complexity and the common use of complex power management schemes increase the likelihood of an unknown ‘X’ state in the design translating into a functional bug in the final chip.

This article describes a methodology that enables design and verification engineers to focus on the X states that represent a real risk, and to set aside those which are artifacts of the design process.

The idea is to reduce project time, particularly that spent in simulation, and overcome the limitations inherent in high-level techniques at both RTL and gate level. (more…)

A Night to Remember: EDA Back to the Future

Thursday, October 17th, 2013

I had the pleasure to attend the EDA: Back to the Future event at the Computer History Museum last night.   There were over 230 guests to raise money for the EDA Oral History Project at the Museum.   There were industry luminaries honored at the event, and I did red carpet interviews with many of them as they arrived including Joe Costello, Simon Segars, and Penny Herscher.   If you would like to know more about the Museum project watch this very cool video that was shown to the attendees:

 

You can make a gift donation to the Computer History Museum in support of the EDA Oral History Project by following the link here.

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EETimes DesignLine: An Engineer’s Progress With Prakash Narain, Part 4

Monday, October 14th, 2013

Brian Bailey, Engineering Consultant & EETimes DesignLine contributing editor, recently did an in-depth interview of Prakash Narain, CEO of Real Intent about his career in EDA.  In this last of a four part blog series,  Prakash talks about listening, SoC sign-off and the Internet of Things.

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EETimes DesignLine: An Engineer’s Progress, With Prakash Narain, Part 3

Thursday, October 10th, 2013

Brian Bailey, Engineering Consultant & EETimes DesignLine contributing editor, recently did an in-depth interview of Prakash Narain, CEO of Real Intent about his career in EDA.  In this third of a four part blog series,  Prakash reveals why Real Intent changed its focus, the role of static verification and if there are any regrets.

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EETimes DesignLine: An Engineer’s Progress With Prakash Narain, Part 2

Monday, October 7th, 2013

Brian Bailey, Engineering Consultant & EETimes DesignLine contributing editor, recently did an in-depth interview of Prakash Narain, CEO of Real Intent about his career in EDA.  In this second of a four part blog series,  Prakash reveals why he has grey hair, the role of mentors and that the company’s first product was an accidental discovery.

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EETimes DesignLine: An Engineer’s Progress With Prakash Narain, Part 1

Thursday, October 3rd, 2013

Brian Bailey, Engineering Consultant & EETimes DesignLine contributing editor, recently did an in-depth interview of Prakash Narain, CEO of Real Intent about his career in EDA.  In this first of a four part blog series,  Prakash confesses how EDA is complex, fascinating, and intellectually satisfying but at the same time a little painful.

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