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Graham Bell
Graham Bell
Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »

Clean SoC Initialization now Optimal and Verified with Ascent XV

September 26th, 2013 by Graham Bell

Three weeks ago, I shared a video interview of Pranav Ashar talking about how SoC Sign-off Needs Analysis and Optimization of Design Initialization in the Presence of Xs.  Last week Real Intent announced the latest release of its Ascent XV that address this new sign-off concern.

Analysis and optimization of design initialization in the presence of X’s is a new requirement for SoC sign-off due to modern power-management schemes. Ascent XV provides the necessary analysis of initialization sequences to ensure they are complete and optimal for various power states in an SoC. It provides the same best-in-class verification performance and debug efficiency as our other Ascent products, uncovering issues prior to digital simulation and synthesis.

Ascent XV identifies X-sources and potential X-propagation issues early-on in Verilog RTL or netlist designs. It enables the detection and debug of functional issues caused by X-optimism at RTL, prior to synthesis. It also eliminates unnecessary X’s caused by X-pessimism at the netlist. Ascent XV analysis can catch issues prior to RTL sign-off, driving costs down and avoiding monotonous, error-prone debug at the netlist level.

Notable features for the new Ascent XV release include:

  •  Initialization analysis that reports flops and latches uninitialized after the reset sequence
  • Reset and retention-flop optimization that ensures complete initialization with minimal hardware and routing requirements for savings in area and power
  • Hazard analysis that reports design susceptibility to X-hazards, and automatically detects and reports all X-sources in the design
  • SimPortal that enables Verilog simulation to detect and debug real X-optimism issues, and to model low power retention cells at RTL
  • A debugger that correlates X-optimistic and X-pessimistic signals to X-sources

Find out more about Ascent XV here on the Real Intent web-site.


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