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Archive for September 26th, 2013

Clean SoC Initialization now Optimal and Verified with Ascent XV

Thursday, September 26th, 2013

Three weeks ago, I shared a video interview of Pranav Ashar talking about how SoC Sign-off Needs Analysis and Optimization of Design Initialization in the Presence of Xs.  Last week Real Intent announced the latest release of its Ascent XV that address this new sign-off concern.

Analysis and optimization of design initialization in the presence of X’s is a new requirement for SoC sign-off due to modern power-management schemes. Ascent XV provides the necessary analysis of initialization sequences to ensure they are complete and optimal for various power states in an SoC. It provides the same best-in-class verification performance and debug efficiency as our other Ascent products, uncovering issues prior to digital simulation and synthesis.

Ascent XV identifies X-sources and potential X-propagation issues early-on in Verilog RTL or netlist designs. It enables the detection and debug of functional issues caused by X-optimism at RTL, prior to synthesis. It also eliminates unnecessary X’s caused by X-pessimism at the netlist. Ascent XV analysis can catch issues prior to RTL sign-off, driving costs down and avoiding monotonous, error-prone debug at the netlist level.

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