On Sept. 12, Real Intent, announced significant enhancements for our Ascent Lint product, which we claim is the industry’s fastest and most accurate tool RTL lint Analyzer and rule checker. It handles 500M gate designs in just minutes and so it is easy to find errors prior to Verilog or VHDL simulation, leading to improved quality of results (QoR) and higher design team productivity.
The new 2013 version of Ascent Lint delivers enhanced support for SystemVerilog, Verilog and VHDL languages, and improves ease of use in the GUI and low-noise reporting of design issues. A new integrated Emacs-mode feature enables users to view and manage all lint violations at each RTL source location for easier debugging. Users now can edit the source code, manage violations, and rerun Ascent Lint to view updated violations – all from within the Emacs editor.
Further notable enhancements and new features for Ascent Lint include:
- 22 new lint rules that ensure design code quality and consistency for a wide range of potential issues
- A new CDC Readiness policy to ensure that the design is ready for Clock Domain Crossing analysis
- Extension of regular expression syntax to be Perl-compatible for more flexible processing
- Enhanced RTL analysis, processing and selection of source and library files
- Comparison of separate analysis reports to expose differences and changes
For more information about the new enhancements for Ascent Lint 2013, please watch this short (3 minute) video by Shiva Borzin, Technical Marketing Manager at Real Intent. (more…)