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Archive for September 5th, 2013

SoC Sign-off Needs Analysis and Optimization of Design Initialization in the Presence of Xs

Thursday, September 5th, 2013

For today’s SoCs, modern power management schemes affect how designs are reset (started). X management and reset analysis are interrelated because many of the X’s in simulation come from uninitialized flip-flops and, conversely, the pitfalls of X’s in simulation compromise the ability to arrive at a clear understanding of the resetability of a design.

In the video interview below, Pranav Ashar, CTO at Real Intent, points out how verification sign-off now must include analysis of reset and design initialization to ensure it is correct and optimal for various power modes in an SoC.

S2C: FPGA Base prototyping- Download white paper

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