Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
Semi Design Technology & System Drivers Roadmap: Part 5 – Low Power
August 29th, 2013 by Graham Bell
Andrew B. Kahng, Professor of CSE and ECE, Univ. of California at San Diego presented a paper on “The ITRS Design Technology and System Drivers Roadmap: Process and Status” at the 50th Design Automation Conference in Austin, TX. This important review of the technology challenges that are in front of the EDA industry and what is the current status is presented here below in this fifth part of a blog series.
5. LOW-POWER DESIGN
In response to power and energy being identiﬁed as the grand challenge for the semiconductor roadmap, the Design TWG in 2011 added a Low-Power Design technology roadmap to the Design Chapter. The low-power design roadmap contains a mix of future solutions spanning electrical, functional and software realms . Projected low-power design innovations include (i) frequency islands and near-threshold computing at the circuit level; (ii) heterogeneous parallel processing, many core software development tools, and hardware/software co-partitioning at the architecture level; and (iii) power-aware software and software virtual prototyping at the software level. Figure 8 shows that with low-power innovations the SOC-CP driver dissipates 3.5W (with 48.8M logic gates) in 2011. Low-power design innovations will help limit the power to 8.22W when the number of logic gates grows by more than 40x to 1995.5M in 2026.
Figure 8 shows that even if future low-power innovations are developed and deployed according to the low-power design roadmap, power of mobile SOC-CP designs will keep increasing. This is unacceptable in the mobile context; indeed, the SOC-CP driver has a ﬂat power consumption requirement of ∼2W through the end of the roadmap. This is not a new story: Figure 7 from the 2001 Design Chapter predicts that percentage of logic that can be turned on reduces steadily to 2%-6% around 2012, i.e., what researchers have recently termed “dark silicon” , . The inability to manage power limits the amount of (switched) logic content in an SOC, which in turn limits product value.
In 2012, new additions to the low-power design roadmap include (i) approximate computing (variable-accuracy computing, e.g., ﬂexibly from 64b to 16b); (ii) 4D computing (reconﬁguration of circuits on the ﬂy); and (iii) adaptivity (recapturing overdesign due to wearout and variation margins, etc.). To manage power to extreme limits, future low-power innovations must also improve the accuracy of power modeling and estimation. Chips are becoming heterogeneous systems (complex entities with multi-processor software environments) with unpredictable behavior and performance (more of a chip is turned off at any given moment, i.e., dark silicon). In this context, accurate estimation of chip power becomes very difﬁcult.
 H. Esmaeilzadeh, E. Blem, R. S. Amant, K. Sankaralingam and D. Burger, “Dark Silicon and The End of Multicore Scaling”, Proc. ISCA, 2011, pp. 365-376.
 A. B. Kahng, “The Road Ahead: Roadmapping Power”, IEEE Design and Test of Computers, 28(5) (2011), pp. 104-106.
 G. Venkatesh, J. Sampson, N. Goulding, S. Garcia, V. Bryksin, J. Lugo-Martinez, S. Swanson and M. B. Taylor, “Conservation Cores: Reducing the Energy of Mature Computations”, Proc. ASPLOS, 2010, pp. 205-218.
 “GlobalFoundries Details 14nm-XM FinFET Technology Performance, Power and Area Efﬁciency with a Dual-Core Cortex-A9 Processor Implementation”. http://www.globalfoundries.com/newsroom/2013/20130205-ARM.aspx
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