Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
Semiconductor Design Technology and System Drivers Roadmap: Process and Status – Part 4
August 15th, 2013 by Graham Bell
Andrew B. Kahng, Professor of CSE and ECE, Univ. of California at San Diego presented a paper on “The ITRS Design Technology and System Drivers Roadmap: Process and Status” at the 50th Design Automation Conference in Austin, TX. This important review of the technology challenges that are in front of the EDA industry and what is the current status is presented here below in this fourth part of a blog series.
4. LAYOUT DENSITY A-FACTORS
In the ITRS System Drivers Chapter and Overall Roadmap Technology Characteristics, A-factors enable the modeling of unit cell areas of SRAM and standard-cell logic circuit fabrics, in terms of the M1 half-pitch, F . SRAM layout density is mainly determined by Mx pitches and poly pitch in a bulk technology. With FinFET devices, the fin pitch ( Pfin ) becomes the dominant factor for SRAM layout. On the other hand, the density of standard cells is mainly decided by the cell height (in M2 tracks) and the poly pitch. Since the 2009 ITRS, the A-factor for a 6T SRAM bitcell has been 60 sq. F, and the A-factor for a 2-input NAND gate has been 175 sq. F . These values are based on various ratios between, e.g., poly, M1, and M2 layer pitches (design rules) as summarized in the left half of Table 1, as well as on the canonical layouts shown in Figures 4(b) and 5(b) .
As the industry moves to double-patterning, FinFETs with discrete gate widths, and “middle of line” (MOL) layers to enable local access to transistors, the fundamental A-factor scaling models will likely require significant revisions. For example, in future NAND2 cell layouts, M1 may no longer be the most congested metal layer, so M2 pitch ( PM2 ) may shrink to be the same as M1 pitch ( PM1 ). Furthermore, with emerging FinFET (multi-gate) devices, fin pitch ( Pfin ) cannot be arbitrarily small, and gate width is in quanta of fins. Based on these considerations, the A-factor of the bulk NAND2 layout may evolve to 144 sq. F (Figure 4(b)), i.e., Wcell = 3Ppoly , Hcell = 8PM2 , and hence ABulk,NAND2 = Wcell × Hcell = 144 sq. F. The area of the FinFET NAND2 layout may be set to 162 sq. F (Figure 4(a)), i.e., Wcell = 3Ppoly , Hcell = 9PM2 , and hence AFinFET,NAND2 = Wcell × Hcell = 162 sq. F. See footnote 1. Industry colleagues have observed that contacted poly pitch (CPP) appears more difficult to scale than Mx (local metal) pitch. In other words, Mx pitch seems to be scaling at a rate faster than 0.7 × per node, while CPP scales at a rate slower than 0.7 × per node, even as the product of the two pitches achieves 0.5 × area scaling. Such a trend, if continued, may eventually change the A-factor modeling and A-factor values.
Figures 5(a) and (b) respectively give canonical layouts for FinFET and bulk 6T SRAM bitcells. Each layout uses two poly channels, so the bitcell height is 2Ppoly . The width of the bitcell depends on (i) the distances between bitline to wordline on each end; (ii) transistor separations (P to N); and (iii) distance between n-active (N to N); these parameters differ for FinFET and bulk. The width of the 6T bulk SRAM is 5PM1 from Figure 5(b), and the A-factor of the bulk 6T SRAM is therefore 60 sq. F .
Derivation of an A-factor for a FinFET-based 6T SRAM bitcell must consider two main issues. First, a pitch conversion between Pfin , PM1 and Ppoly must be determined; industry experts suggest Pfin = 0.75 × PM1 . Second, the β ratio (i.e., the ratio of fin counts between the PU and PD transistors in FinFET SRAM bitcell) is critical for read stability [9,16], and affects fin counts and layout. For example, using a β ratio of 2 along with the pitch ratios in Table 1 would set the width of routing regions of bitlines to 2 × 0.75 Pfin , PD NMOS to 2 × Pfin , P/N channel separation to 2 × 1.5Pfin , and PU PMOS to 1 × Pfin . The A-factor of the FinFET 6T SRAM would then be calculated as 67 sq. F. (Note that the area overhead can be less in 8T FinFET bitcells compared to 6T FinFET bitcells, since additional read transistors in 8T bitcells provide read margin protection. By assuming β = 1 . 0 and the layout in Figure 6, the A-factor of 8T FinFET SRAM would be calculated as 72 sq. F.)
 Z. Guo, S. Balasubramanian, R. Zlatanovici, T.-J. King and B. Nikolic, “FinFET-Based SRAM Design”, Proc. ISLPED, 2005, pp. 2-7.
 K. Jeong and A. B. Kahng, “A Power-Constrained MPU Roadmap for the International Technology Roadmap for Semiconductors (ITRS)”, Proc. ISOCC, 2009, pp. 49-52.
 D. Lekshmanan, A. Bansal and K. Roy, “FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve Stability at Iso Area”, Proc. CICC, 2007, pp. 623-626.
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