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Archive for August 15th, 2013

Semiconductor Design Technology and System Drivers Roadmap: Process and Status – Part 4

Thursday, August 15th, 2013
Andrew B. Kahng, Professor of CSE and ECE, Univ. of California at San Diego presented a paper on “The ITRS Design Technology and System Drivers Roadmap: Process and Status” at the 50th Design Automation Conference in Austin, TX.   This important review of the technology challenges that are in front of the EDA industry and what is the current status is presented here below in this fourth part of a blog series.

4. LAYOUT DENSITY A-FACTORS

In the ITRS System Drivers Chapter and Overall Roadmap Technology Characteristics, A-factors enable the modeling of unit cell areas of SRAM and standard-cell logic circuit fabrics, in terms of the M1 half-pitch, F . SRAM layout density is mainly determined by Mx pitches and poly pitch in a bulk technology. With FinFET devices, the fin pitch ( Pfin ) becomes the dominant factor for SRAM layout. On the other hand, the density of standard cells is mainly decided by the cell height (in M2 tracks) and the poly pitch. Since the 2009 ITRS, the A-factor for a 6T SRAM bitcell has been 60 sq. F, and the A-factor for a 2-input NAND gate has been 175 sq. F [10]. These values are based on various ratios between, e.g., poly, M1, and M2 layer pitches (design rules) as summarized in the left half of Table 1, as well as on the canonical layouts shown in Figures 4(b) and 5(b) [10].

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