Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
Semiconductor Design Technology and System Drivers Roadmap: Process and Status – Part 3
August 8th, 2013 by Graham Bell
Andrew B. Kahng, Professor of CSE and ECE, Univ. of California at San Diego presented a paper on “The ITRS Design Technology and System Drivers Roadmap: Process and Status” at the 50th Design Automation Conference in Austin, TX. This important review of the technology challenges that are in front of the EDA industry and what is the current status is presented here below in this third part of a blog series.
3. KEY SYSTEM DRIVER MODELS
As noted above, the System Drivers Chapter models and projects key semiconductor product classes that create the need for continued semiconductor innovation [5–7]. The 2011 System Drivers Chapter identifies three microprocessor (MPU) drivers (high-performance (HP), cost-performance (CP) and power-connectivity-cost (PCC)) and three System-On-Chip (SOC) drivers (consumer portable (CP), consumer stationary (CS) and networking (NW)). See footnote 1. Each driver should provide impetus for specific technology objectives, e.g., the SOC-CP driver drives lower leakage (or standby) power consumption, given the severe battery life requirement of mobile devices. For each MPU and SOC system driver, the ITRS roadmaps scaling of parameters such as number of cores, number of SRAM and logic transistors, layout density, frequency and power.
MPU Driver Modeling
The ITRS MPU driver model has for many years scaled the number of logic transistors and the number of SRAM transistors by 2× per technology node. Since dimensions shrink by 0.7× per node, and nominal layout density therefore doubles, this simple scaling model allows die size to remain constant across technology nodes.
MPU Die Size. The 2009 MPU model update  set a constant die area of 260 sq. mm for MPU-HP and 140 sq. mm for MPU-CP. The model for logic density (D tr,logic ) is
where N tr,nand2 (number of transistors in a NAND2 gate) is four, O logic (logic overhead due to design integration) is 2.0 (i.e., 100% area overhead for whitespace), and U logic (the area of a unit NAND2 gate) is calculated using the “A-factor” described below in Section 4. The model for SRAM density ( D tr,SRAM )  is
where N tr,bitcell is the number of transistors in a SRAM bitcell, O SRAM (overhead due to peripheral circuits) is assumed to be 1.6 (i.e., 60% area overhead), and U SRAM (the area of a unit SRAM bit- cell) is calculated using another A-factor, also described in Section 4. While the 2009 MPU model remains accurate with respect to number of cores, or total number of transistors, die areas of recent server MPU products have grown rapidly, reaching ∼ 530 sq. mm in the 2012-2013 time frame. Moreover, the simple model of cores + SRAM does not acknowledge the growth of “uncore” elements (memory controllers, IO controllers, GPU cores, on-chip networking, etc.) in MPU products. These considerations make it likely that the 2013 ITRS edition will see substantial revision of the MPU-HP model with respect to both A-factors and architecture.
MPU Frequency. Figure 3 overlays historical changes in the ITRS maximum on-chip frequency roadmap with product data from the Stanford CPUDB . The 2001 System Drivers Chapter observed that rapid MPU frequency increases up to that time had been enabled by reduction in the number of fanout-of-four (FO4) delays per clock period. That is, microarchitecture (aggressive pipelining, with fewer stages of logic per pipeline stage) had been used to increase frequency at a faster rate than the intrinsic growth of device switching speed. At that time (2001), a basic limit of 12 FO4 delays (in which useful computation could be performed during a clock cycle) was being reached, and so the roadmap was modified to improve frequency only as device speeds improved (17%/year improvement in CV/I metric, in the PIDS roadmap).
In 2007, a market-driven platform power limit of 130W per die was acknowledged, and the MPU frequency roadmap was revised to increase by just 8% per year to meet this power limit. See footnote 2. The slowing of frequency enabled the PIDS device roadmap to also slow the CV/I improvement to 13%/year, which eased the challenge of managing leakage currents. Subsequently, during the 2009-2011 roadmapping cycle, device technologists found that even the 13%/year CV/I improvement was incompatible with leakage current requirements; hence, the likely scenario for 2013 and beyond is for 4%/year frequency increase in MPU products (still with design-based equivalent scaling in the form of switching factor reductions), along with some limited “headroom” of 8%/year improvement in the device CV/I metric.
System Driver Futures
During the 12 years since the System Drivers Chapter was introduced, many structural changes have occurred in the marketplace. As these shifts occur, the set of system drivers, and their intrinsic models, are subject to change.
 J.-A. Carballo and A. B. Kahng, “ITRS Chapters: Design and System Drivers”, Future Fab International (36) (2011), pp. 45-48.
 J.-A. Carballo and A. B. Kahng, “ITRS Chapters: Design and System Drivers”, Future Fab International (40) (2012), pp. 54-59.
 J.-A. Carballo and A. B. Kahng, “ITRS Chapters: Design and System Drivers”, Future Fab International (44) (2013), pp. 52-56.
 K. Jeong and A. B. Kahng, “A Power-Constrained MPU Roadmap for the International Technology Roadmap for Semiconductors (ITRS)”, Proc. ISOCC, 2009, pp. 49-52.
 CPUDB. http://cpudb.stanford.edu/
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