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Archive for August 8th, 2013

Semiconductor Design Technology and System Drivers Roadmap: Process and Status – Part 3

Thursday, August 8th, 2013

Andrew B. Kahng, Professor of CSE and ECE, Univ. of California at San Diego presented a paper on “The ITRS Design Technology and System Drivers Roadmap: Process and Status” at the 50th Design Automation Conference in Austin, TX.   This important review of the technology challenges that are in front of the EDA industry and what is the current status is presented here below in this third part of a blog series.


As noted above, the System Drivers Chapter models and projects key semiconductor product classes that create the need for continued semiconductor innovation [5–7]. The 2011 System Drivers Chapter identifies three microprocessor (MPU) drivers (high-performance (HP), cost-performance (CP) and power-connectivity-cost (PCC)) and three System-On-Chip (SOC) drivers (consumer portable (CP), consumer stationary (CS) and networking (NW)). See footnote 1. Each driver should provide impetus for specific technology objectives, e.g., the SOC-CP driver drives lower leakage (or standby) power consumption, given the severe battery life requirement of mobile devices. For each MPU and SOC system driver, the ITRS roadmaps scaling of parameters such as number of cores, number of SRAM and logic transistors, layout density, frequency and power.


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