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Graham Bell
Graham Bell
Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »

Semiconductor Design Technology and System Drivers Roadmap: Process and Status – Part 2

July 25th, 2013 by Graham Bell

Andrew B. Kahng, Professor of CSE and ECE, Univ. of California at San Diego presented a paper on “The ITRS Design Technology and System Drivers Roadmap: Process and Status” at the 50th Design Automation Conference in Austin, TX.   This important review of the technology challenges that are in front of the EDA industry and what is the current status is presented here below in this second part of a blog series.


Like every other technology working group in the ITRS, the Design TWG places the interests of its industry and R&D community – i.e., EDA and VLSI CAD – first and foremost. In ITRS cross-TWG interactions, the Design TWG must respond to questions such as “How much variability can designers tolerate?” (Lithography TWG) or “What is the Jmax limit for on-chip global interconnects?” (Interconnect TWG) or “What tradeoff between leakage and drive currents is best for mobile SOCs?” (Process Integration, Devices and Structures (PIDS) TWG). The roadmap for DFT is jointly owned with the Test TWG. The roadmap for off-chip IO bandwidth is jointly owned with the Test TWG and the Assembly and Packaging (A&P) TWG. And the roadmap for 3D/TSV based integration is jointly owned with a number of other TWGs, notably A&P, Test, Interconnect and Front-End Processing (FEP). All of these interactions entail asynchronous, off-line dialogues year-round with designers, EDA technologists and researchers so that perspectives from IC design, and from IC design automation, are correctly represented.

ITRS challenges and technology requirements directly inform the research priorities and funding allocations of a number of government funding agencies and industry consortia worldwide, and the phrase “According to the ITRS, …” is often given as motivation in academic research papers. Thus, Design TWG activities often include advocacy for the importance of EDA technology and academic research. Furthermore, “key messages” in the Design Chapter can seed future trends in academic research and research funding. Three examples of such advocacy and messaging are as follows.

  • The Design Cost Model. Although tremendous product differentiation comes from design and design technology, EDA industry revenues, and levels of R&D investment and academic research funding, have been stagnant. With this in mind, quantifying the value of design technology has been one of the high-level goals for the Design TWG within the ITRS effort. Since 2001, the Design Chapter has included a highly influential Design Cost model [14] [12] that now encompasses both hardware and software development costs (salary and overhead of engineers, EDA tool cost per seat, interoperability costs, etc.). The cost model quantifies the impact of design technology innovation and resulting productivity improvements. For example, the hardware design costs for a consumer portable SOC design in 2011 are es-timated at $25.7M, versus $7708M had design technology innovations between 1993 and 2009 not occurred.
  • Key Messages. Over the years, the Design TWG has formulated specific key messages within the ITRS. Since 2001, an overarching message has been that “cost of design is the greatest obstacle to continuation of semiconductor roadmap”. In the 1998-2001 time frame, the Design TWG also advocated a “Living ITRS” mindset wherein all technology roadmap projections and models could be implemented on a common platform, to enable interoperability and cross-checking for consistency. See footnote 1. More specific messages have also been given over the years. For example, in 2009 the Design Chapter’s  key messages were that (i) software and system-level design productivity are critical to the roadmap of semiconductor value; (ii) design reliability roadmapping was a necessary addition to the roadmap; (iii) system-level design techniques would ultimately be crucial to managing power; and (iv) design technology innovations must keep on schedule through the end of the roadmap in order to contain design costs. New messages in 2011 and 2012 included (i) roadmapping focus at the design-manufacturing interface has evolved from “manufacturability” to a more general “variability”, which now entails an even broader question of how systems will maintain reliability and be resilient; (ii) design technology innovations must keep on schedule through the end of the roadmap in order to contain power; and (iii) the importance of cross-TWG interactions is continually growing, whether for More Than Moore, 3D, Beyond CMOS, or even the basic device and lithography roadmaps.
  • Grand Challenges. The ITRS Executive Summary calls out a subset of each working group’s “difficult challenges”, and categorizes these as either “Enhancing Performance” or “Cost-Effective Manufacturing”, and as either near-term (within the next seven years) or long-term (between eight and 15 years out). In the 2005-2011 ITRS editions, power management, design productivity, and DFM were consistently listed as near-term grand challenges for design. The roadmap noted that power management challenges would need to be addressed across multiple levels, especially system, design, and process technology. Moreover, to maintain design quality in advanced process nodes, design implementation productivity must improve to the same degree that design complexity is scaled – with improvement of design productivity and IP reuse being key considerations. Long term challenges have evolved from management of leakage power consumption in the 2005-2009 roadmaps to design of concurrent software and design for reliability and resilience in the 2011 roadmap.

The Design TWG operates in a distributed manner, with each major Design Chapter section or System Driver model maintained by a distinct subteam. Different geographies tend to assume natural responsibilities for content, e.g., European contributors have responsibility for the AMS/RF content, and Japanese contributors have responsibility for the SOC system driver models. New content is constantly developed according to identified gaps in roadmap coverage, e.g., Design Chapter updates in 2009 and 2011 include (i) a 3D/TSV design technology section, (ii) a hardware-related software development cost component for Design Cost model, and (iii) a low-power design technology roadmap. Following ITRS convention, the U.S. TWG co-chairs coordinate worldwide efforts and serve as the editors for all published content. See footnote 2.


  1. The GTX (MARCO GSRC Technology Extrapolation) package [4] for some years provided a realization of this goal, but is no longer maintained.
  2. Resources and dedicated bandwidth in support of the ITRS have not yet recovered from the 2008-2009 economic downturn. All suggestions, participation in ITRS
    meetings, and other contributions are always welcome; interested individuals should contact the Design TWG co-chairs, Dr. Andrew B. Kahng ( and Dr. Juan-Antonio Carballo (


[4] A. E. Caldwell, Y. Cao, A. B. Kahng, F. Koushanfar, H. Lu, I. L.Markov, M. R. Oliver, D. Stroobandt and D. Sylvester, “GTX: TheMARCO GSRC Technology Exploration System”,Proc. DAC, 2000, pp. 693-698.

[12] A. B. Kahng, “The Road Ahead: The cost of design”, IEEE Design and Test, 19(4) (2002), pp. 136-137.

[14] A. B. Kahng and G. Smith, “A New Design Cost Model for the 2001 ITRS”, Proc. ISQED, 2002, pp. 190-193.

[21] iNEMI.

[22] ITRS Edition Reports.

Copyright Notice

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. DAC’13, May 29 – June 07 2013, Austin, TX, USA. Copyright 2013 ACM 978-1-4503-2071-9/13/05 …$15.00.

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