Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
Semiconductor Design Technology and System Drivers Roadmap: Process and Status – Part 2
July 25th, 2013 by Graham Bell
Andrew B. Kahng, Professor of CSE and ECE, Univ. of California at San Diego presented a paper on “The ITRS Design Technology and System Drivers Roadmap: Process and Status” at the 50th Design Automation Conference in Austin, TX. This important review of the technology challenges that are in front of the EDA industry and what is the current status is presented here below in this second part of a blog series.
2. DESIGN TECHNOLOGY WORKING GROUP GOALS AND PROCESS
Like every other technology working group in the ITRS, the Design TWG places the interests of its industry and R&D community – i.e., EDA and VLSI CAD – first and foremost. In ITRS cross-TWG interactions, the Design TWG must respond to questions such as “How much variability can designers tolerate?” (Lithography TWG) or “What is the Jmax limit for on-chip global interconnects?” (Interconnect TWG) or “What tradeoff between leakage and drive currents is best for mobile SOCs?” (Process Integration, Devices and Structures (PIDS) TWG). The roadmap for DFT is jointly owned with the Test TWG. The roadmap for off-chip IO bandwidth is jointly owned with the Test TWG and the Assembly and Packaging (A&P) TWG. And the roadmap for 3D/TSV based integration is jointly owned with a number of other TWGs, notably A&P, Test, Interconnect and Front-End Processing (FEP). All of these interactions entail asynchronous, off-line dialogues year-round with designers, EDA technologists and researchers so that perspectives from IC design, and from IC design automation, are correctly represented.
ITRS challenges and technology requirements directly inform the research priorities and funding allocations of a number of government funding agencies and industry consortia worldwide, and the phrase “According to the ITRS, …” is often given as motivation in academic research papers. Thus, Design TWG activities often include advocacy for the importance of EDA technology and academic research. Furthermore, “key messages” in the Design Chapter can seed future trends in academic research and research funding. Three examples of such advocacy and messaging are as follows.
The Design TWG operates in a distributed manner, with each major Design Chapter section or System Driver model maintained by a distinct subteam. Different geographies tend to assume natural responsibilities for content, e.g., European contributors have responsibility for the AMS/RF content, and Japanese contributors have responsibility for the SOC system driver models. New content is constantly developed according to identified gaps in roadmap coverage, e.g., Design Chapter updates in 2009 and 2011 include (i) a 3D/TSV design technology section, (ii) a hardware-related software development cost component for Design Cost model, and (iii) a low-power design technology roadmap. Following ITRS convention, the U.S. TWG co-chairs coordinate worldwide efforts and serve as the editors for all published content. See footnote 2.
 A. E. Caldwell, Y. Cao, A. B. Kahng, F. Koushanfar, H. Lu, I. L.Markov, M. R. Oliver, D. Stroobandt and D. Sylvester, “GTX: TheMARCO GSRC Technology Exploration System”,Proc. DAC, 2000, pp. 693-698.
 A. B. Kahng, “The Road Ahead: The cost of design”, IEEE Design and Test, 19(4) (2002), pp. 136-137.
 A. B. Kahng and G. Smith, “A New Design Cost Model for the 2001 ITRS”, Proc. ISQED, 2002, pp. 190-193.
 iNEMI. http://www.inemi.org
 ITRS Edition Reports. http://public.itrs.net/reports.html
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