Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
Semiconductor Design Technology and System Drivers Roadmap: Process and Status – Part 1
July 18th, 2013 by Graham Bell
Andrew B. Kahng, Professor of CSE and ECE, Univ. of California at San Diego presented a paper on “The ITRS Design Technology and System Drivers Roadmap: Process and Status” at the 50th Design Automation Conference in Austin, TX. This important review of the technology challenges that are in front of the EDA industry and what is the current status is presented here below in this first part of a blog series.
The Design technology working group (TWG) is one of 16 working groups in the International Technology Roadmap for Semiconductors (ITRS) effort. It is responsible for the ITRS’ Design Chapter, which roadmaps design technology requirements and potential solutions for elements of the semiconductor supply chain that are produced by the electronic design automation (EDA) industry. The Design TWG is also responsible for the ITRS’ System Drivers Chapter, which roadmaps the key product classes that drive the leading-edge requirements for process and design technologies. Through these activities, the Design TWG sets a number of fundamental parameters in the overall ITRS: layout density, die size, maximum on-chip clock frequency, total chip power, SOC and MPU architecture models, etc. This paper reviews the process by which the Design TWG evolves its roadmap content, and some of the key modeling and roadmapping questions that the semiconductor and EDA industries will face in the near term.
As noted in , technology roadmaps seek “precompetitive” specifications of future technical requirements and challenges. Potential solutions are identified, investigated, pruned, productized, standardized, and delivered to the marketplace – in a synchronized, timely, and cost-effective manner – to ensure a continued stream of technology benefits. The International Technology Roadmap for Semiconductors (ITRS)  is one of the most successful roadmapping efforts ever: well over 1000 scientists and engineers worldwide collaborate to synchronize a wide range of industries and technologies (automated test equipment, assembly and packaging, photomask, electronic design automation (EDA), lithography, interconnect, device, etc.) so that the “Moore’s Law” semiconductor value proposition can continue. The broad scope of the ITRS is essential, e.g., the roadmap for design technology must comprehend (i) lithography and restricted design rules; (ii) die stacking and 3D integration; (iii) device and interconnect electrical performance, variability and robustness; (iv) ATE, BIST and BISR overheads and production costs; (v) product-level trajectories for RF blocks, IO bandwidth and processing capability; and many other futures. The ITRS’s 15-year horizon reflects the lead times needed to identify and develop production-worthy technologies. All technology roadmaps struggle with the tension between “roadmapping” and “extrapolation”. An uncalibrated roadmap lacks credibility. On the other hand, unthinking extrapolation from historical data risks “driving by the rear-view mirror”, and can result in absurd projections at the 15-year horizon. Meaningful roadmapping of technology requirements and potential solutions requires at least the following elements.
The ITRS Design Technology Working Group
The Design technology working group (TWG) is one of 16 TWGs in the ITRS. With over 50 industry and academic contributors from all five regional semiconductor industry associations (USA, EU, Japan, Taiwan, Korea), the Design TWG is responsible for the ITRS Design Chapter, which roadmaps design technology requirements and potential solutions relevant to the EDA industry, and the ITRS System Drivers Chapter, which roadmaps the key product classes that drive leading-edge requirements for process and design technologies. Figure 1 shows how the Design and System Drivers chapters have consistently evolved over the past decade.First, the Design Chapter gives a quantified Design Technology roadmap with metrics, potential solutions, and mappings from requirements to potential solutions. This matches the structure and metrics-oriented “look and feel” of other ITRS chapters. Second, an increasingly comprehensive set of System Drivers has been developed that maintain alignment to key segments of the semiconductor industry. Each update to the System Drivers (e.g., the acknowledgment of a hard platform power limit in the MPU roadmap, starting in 2007) has ripple effects across Overall Roadmap Technology Characteristics (ORTCs) such as layout density, transistor count, die size, chip power and frequency – as well as fundamental technology metrics owned by other technology working groups. These interactions are conceptually depicted in Figure 2. See footnote 2.
The System Drivers also enable stronger alignment (cf. “More Than Moore”) between the ITRS’s chip-level roadmap and system product-level roadmaps such as iNEMI .
Organization of This Paper.
The remainder of this paper is organized as follows. Section 2 outlines the process and overarching objectives that guide the evolution of Design and System Drivers content. Several examples then give the “flavor” of how the roadmap evolves. Two aspects of the System Drivers Chapter are the System Driver model evolution, which is discussed in Section 3, and the “A-factor” approach that underlies projection of density scaling in the ITRS, which is discussed in Section 4. Two aspects of the Design Chapter are the low-power design technology roadmap, which is discussed in Section 5, and the evolution of Design for Manufacturability (Variability, Reliability) content, which is discussed in Section 6. Section 7 concludes with some thoughts on modeling and roadmapping issues that the semiconductor and EDA industries will face in the near term.
 T.-B. Chan and A. B. Kahng, “Tunable Sensors for Process-Aware Voltage Scaling”, Proc. ICCAD, 2012, pp. 7-14.
 A. B. Kahng, “The Road Ahead: Shared Red Bricks”, IEEE Design and Test of Computers, 19(2) (2002), pp. 70-71.
 A. B. Kahng, “The Road Ahead: Roadmapping Power”, IEEE Design and Test of Computers, 28(5) (2011), pp. 104-106.
 iNEMI. http://www.inemi.org
 ITRS Edition Reports. http://public.itrs.net/reports.html
 Design-Based “Equivalent Scaling” to the Rescue of Moore’s Law.
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