Open side-bar Menu
 Real Talk
Graham Bell
Graham Bell
Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »

Semiconductor Design Technology and System Drivers Roadmap: Process and Status – Part 1

 
July 18th, 2013 by Graham Bell

Andrew B. Kahng, Professor of CSE and ECE, Univ. of California at San Diego presented a paper on “The ITRS Design Technology and System Drivers Roadmap: Process and Status” at the 50th Design Automation Conference in Austin, TX.   This important review of the technology challenges that are in front of the EDA industry and what is the current status is presented here below in this first part of a blog series.

The Design technology working group (TWG) is one of 16 working groups in the International Technology Roadmap for Semiconductors (ITRS) effort. It is responsible for the ITRS’ Design Chapter, which roadmaps design technology requirements and potential solutions for elements of the semiconductor supply chain that are produced by the electronic design automation (EDA) industry. The Design TWG is also responsible for the ITRS’ System Drivers Chapter, which roadmaps the key product classes that drive the leading-edge requirements for process and design technologies. Through these activities, the Design TWG sets a number of fundamental parameters in the overall ITRS: layout density, die size, maximum on-chip clock frequency, total chip power, SOC and MPU architecture models, etc. This paper reviews the process by which the Design TWG evolves its roadmap content, and some of the key modeling and roadmapping questions that the semiconductor and EDA industries will face in the near term.

1. INTRODUCTION

As noted in [13], technology roadmaps seek “precompetitive” specifications of future technical requirements and challenges. Potential solutions are identified, investigated, pruned, productized, standardized, and delivered to the marketplace – in a synchronized, timely, and cost-effective manner – to ensure a continued stream of technology benefits. The International Technology Roadmap for Semiconductors (ITRS) [22] is one of the most successful roadmapping efforts ever: well over 1000 scientists and engineers worldwide collaborate to synchronize a wide range of industries and technologies (automated test equipment, assembly and packaging, photomask, electronic design automation (EDA), lithography, interconnect, device, etc.) so that the “Moore’s Law” semiconductor value proposition can continue. The broad scope of the ITRS is essential, e.g., the roadmap for design technology must comprehend (i) lithography and restricted design rules; (ii) die stacking and 3D integration; (iii) device and interconnect electrical performance, variability and robustness; (iv) ATE, BIST and BISR overheads and production costs; (v) product-level trajectories for RF blocks, IO bandwidth and processing capability; and many other futures. The ITRS’s 15-year horizon reflects the lead times needed to identify and develop production-worthy technologies. All technology roadmaps struggle with the tension between “roadmapping” and “extrapolation”. An uncalibrated roadmap lacks credibility. On the other hand, unthinking extrapolation from historical data risks “driving by the rear-view mirror”, and can result in absurd projections at the 15-year horizon. Meaningful roadmapping of technology requirements and potential solutions requires at least the following elements.

  • Metrics. What cannot be measured cannot be tracked or improved. EDA tools heuristically address large-scale, NP-hard optimizations, and design quality is strongly determined by flow and methodology (“it’s the magician, not the wand”). Thus, it is challenging to identify metrics that capture the progress of design technology.
  • Understanding of contexts and needs for technology. Contexts ranging from process technology to market forces affect the need for technology. For example, the trajectory of mobile consumer SOC products has driven rapid innovation in low-power design techniques spanning embedded memory design, power and clock gating, dynamic voltage scaling, etc. At the same time, these low-power design techniques must acknowledge process and material attributes such as discreteness of FinFET device widths starting at the 16nm foundry node, or increasingly dominant reliability and aging mechanisms.
  • Holistic selection of potential solutions. Technology roadmapping must holistically model and predict impacts of potential technology solutions, at many levels. For example, solutions to a “power crisis” in IC design may come from manufacturing technologists (e.g., process innovation to reduce Vth variation), device and circuit technologists (introduction of FinFET and resistive RAM), and system designers (heterogeneous multi-core SOC architectures) – as well as design and test technologists (asynchronous design flow, on-chip variability monitoring and adaptivity, etc.). All potential solutions cost money to develop and deploy. Thus, as discussed in [11], a mindset of “shared red bricks” in the semiconductor technology roadmap is critical to achieve proper allocation of R&D resources.  See footnote 1.

The ITRS Design Technology Working Group

The Design technology working group (TWG) is one of 16 TWGs in the ITRS. With over 50 industry and academic contributors from all five regional semiconductor industry associations (USA, EU, Japan, Taiwan, Korea), the Design TWG is responsible for the ITRS Design Chapter, which roadmaps design technology requirements and potential solutions relevant to the EDA industry, and the ITRS System Drivers Chapter, which roadmaps the key product classes that drive leading-edge requirements for process and design technologies. Figure 1 shows how the Design and System Drivers chapters have consistently evolved over the past decade.

Figure 1: Roadmap from ITRS System Drivers and Design chapters. [Source: ITRS Design ITWG 2011 Public Conference presentation, December 2011, Songdo, Korea.]

First, the Design Chapter gives a quantified Design Technology roadmap with metrics, potential solutions, and mappings from requirements to potential solutions. This matches the structure and metrics-oriented “look and feel” of other ITRS chapters. Second, an increasingly comprehensive set of System Drivers has been developed that maintain alignment to key segments of the semiconductor industry. Each update to the System Drivers (e.g., the acknowledgment of a hard platform power limit in the MPU roadmap, starting in 2007) has ripple effects across Overall Roadmap Technology Characteristics (ORTCs) such as layout density, transistor count, die size, chip power and frequency – as well as fundamental technology metrics owned by other technology working groups. These interactions are conceptually depicted in Figure 2. See footnote 2.

Figure 2: Increasingly central role of Design TWG in ITRS roadmap definition.

The System Drivers also enable stronger alignment (cf. “More Than Moore”) between the ITRS’s chip-level roadmap and system product-level roadmaps such as iNEMI [21].

Organization of This Paper.

The remainder of this paper is organized as follows. Section 2 outlines the process and overarching objectives that guide the evolution of Design and System Drivers content. Several examples then give the “flavor” of how the roadmap evolves. Two aspects of the System Drivers Chapter are the System Driver model evolution, which is discussed in Section 3, and the “A-factor” approach that underlies projection of density scaling in the ITRS, which is discussed in Section 4. Two aspects of the Design Chapter are the low-power design technology roadmap, which is discussed in Section 5, and the evolution of Design for Manufacturability (Variability, Reliability) content, which is discussed in Section 6. Section 7 concludes with some thoughts on modeling and roadmapping issues that the semiconductor and EDA industries will face in the near term.

Footnotes

  1. In ITRS parlance, a “red brick” is a technology requirement that has no known solution (the term stems from the coloring convention in ITRS technology requirement tables). For example, to solve the problem of poor interconnect RC scaling, are R&D dollars best invested in new dielectric materials, new interconnect and barrier materials, better overlay control, more accurate signal integrity analyses in EDA tools, scalable many-core GALS architectures, or …? Or, to solve the problem of exploding (and widening) modes and corners in signoff, should variation be reduced in the process itself, or should statistical signoffs be adopted, or should “signoff at typical” be adopted in combination with adaptivity [3], or …?
  2. In over 17 years of NTRS and ITRS roadmap participation, I have witnessed a steady rise in the prominence of “design” within the ITRS. Originally highly process-centric, the roadmap now increasingly relies on “design-based equivalent scaling” [24] and “More Than Moore” to deliver scaling of semiconductor product value in the face of non-ideal performance, power, density and variability scaling.
  3. “More Than Moore” to deliver scaling of semiconductor product value in the face of non-ideal performance, power, density and variability scaling.

References

[3] T.-B. Chan and A. B. Kahng, “Tunable Sensors for Process-Aware Voltage Scaling”, Proc. ICCAD, 2012, pp. 7-14.

[11] A. B. Kahng, “The Road Ahead: Shared Red Bricks”, IEEE Design and Test of Computers, 19(2) (2002), pp. 70-71.

[13] A. B. Kahng, “The Road Ahead: Roadmapping Power”, IEEE Design and Test of Computers, 28(5) (2011), pp. 104-106.

[21] iNEMI. http://www.inemi.org

[22] ITRS Edition Reports. http://public.itrs.net/reports.html

[24] Design-Based “Equivalent Scaling” to the Rescue of Moore’s Law.
http://vlsicad.ucsd.edu/Presentations/talk/UCI-Colloquium-121031-v7-distributed.pdf

Copyright Notice

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. DAC’13, May 29 – June 07 2013, Austin, TX, USA. Copyright 2013 ACM 978-1-4503-2071-9/13/05 …$15.00.

Related posts:

Leave a Reply

Your email address will not be published. Required fields are marked *


*

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <strike> <strong>

CST Webinar Series
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy