In Austin, at the 50th DAC in June, I delivered a poster presentation on “Lending a ‘Formal’ Hand to CDC Verification: A Case Study of Non-Intuitive Failure Signatures”. In this final blog in a series, I discuss the causes for a failure when the counter value of the control logic equals 16 and then look at pulse width results when using both aligned or offset reset signals.
Following a FAIL with counter = 14 and a PASS with counter = 15, here we take a look at a FAIL with counter = 16.
The Control signal is held high by the counter during the second half of the total count of 16 (from 0x8 to 0xf).
Note that when Mux-on is high, the mux is open and the Data signal gets captured in the Rx Data flop.
Take a look at the signals in the vicinity of the two vertical dotted lines on the right. The first dotted line aligns with a change in the Data signal which happens when the counter wraps. Since the mux is open (Mux-on is high) the Data is captured by the Rx Data flop on the first receive clock edge following the change in Data. This is marked by the second dotted line and is a Data Stability failure.
Note that, in order to produce a failing trace in this case, the counter needs to wrap around twice. In order to understand why there is no Data Stability failure in the first full count of the counter, take a look at the Grey oval in the waveforms. When the mux is open (when Mux=on is high), note that the Data remains stable and is not changing. Hence there is no Data Stability issue here.