Open side-bar Menu
 Real Talk

Archive for July, 2013

Semiconductor Design Technology and System Drivers Roadmap: Process and Status – Part 2

Thursday, July 25th, 2013

Andrew B. Kahng, Professor of CSE and ECE, Univ. of California at San Diego presented a paper on “The ITRS Design Technology and System Drivers Roadmap: Process and Status” at the 50th Design Automation Conference in Austin, TX.   This important review of the technology challenges that are in front of the EDA industry and what is the current status is presented here below in this second part of a blog series.

2. DESIGN TECHNOLOGY WORKING GROUP GOALS AND PROCESS

Like every other technology working group in the ITRS, the Design TWG places the interests of its industry and R&D community – i.e., EDA and VLSI CAD – first and foremost. In ITRS cross-TWG interactions, the Design TWG must respond to questions such as “How much variability can designers tolerate?” (Lithography TWG) or “What is the Jmax limit for on-chip global interconnects?” (Interconnect TWG) or “What tradeoff between leakage and drive currents is best for mobile SOCs?” (Process Integration, Devices and Structures (PIDS) TWG). The roadmap for DFT is jointly owned with the Test TWG. The roadmap for off-chip IO bandwidth is jointly owned with the Test TWG and the Assembly and Packaging (A&P) TWG. And the roadmap for 3D/TSV based integration is jointly owned with a number of other TWGs, notably A&P, Test, Interconnect and Front-End Processing (FEP). All of these interactions entail asynchronous, off-line dialogues year-round with designers, EDA technologists and researchers so that perspectives from IC design, and from IC design automation, are correctly represented.

(more…)

Semiconductor Design Technology and System Drivers Roadmap: Process and Status – Part 1

Thursday, July 18th, 2013

Andrew B. Kahng, Professor of CSE and ECE, Univ. of California at San Diego presented a paper on “The ITRS Design Technology and System Drivers Roadmap: Process and Status” at the 50th Design Automation Conference in Austin, TX.   This important review of the technology challenges that are in front of the EDA industry and what is the current status is presented here below in this first part of a blog series.

The Design technology working group (TWG) is one of 16 working groups in the International Technology Roadmap for Semiconductors (ITRS) effort. It is responsible for the ITRS’ Design Chapter, which roadmaps design technology requirements and potential solutions for elements of the semiconductor supply chain that are produced by the electronic design automation (EDA) industry. The Design TWG is also responsible for the ITRS’ System Drivers Chapter, which roadmaps the key product classes that drive the leading-edge requirements for process and design technologies. Through these activities, the Design TWG sets a number of fundamental parameters in the overall ITRS: layout density, die size, maximum on-chip clock frequency, total chip power, SOC and MPU architecture models, etc. This paper reviews the process by which the Design TWG evolves its roadmap content, and some of the key modeling and roadmapping questions that the semiconductor and EDA industries will face in the near term.

(more…)

Executive Video Briefing: Prakash Narain on RTL and SoC Sign-off

Thursday, July 11th, 2013

Real Intent CEO Prakash Narain spoke in June with Ed Sperling, Editor-in-Chief of System-Level Design, about where are the pain points in verification; the different types of sign-off; the impact of third-party IP; and can the tools industry keep up with the rising complexity in semiconductor design. Enjoy!

Lending a ‘Formal’ Hand to CDC Verification: A Case Study of Non-Intuitive Failure Signatures — Part 3

Thursday, July 4th, 2013

In Austin, at the 50th DAC in June,  I delivered a poster presentation on “Lending a ‘Formal’ Hand to CDC Verification: A Case Study of Non-Intuitive Failure Signatures”.   In this final blog in a series, I discuss the causes for a failure when the counter value of the control logic equals 16 and then look at pulse width results when using both aligned or offset reset signals.

Following a FAIL with counter = 14 and a PASS with counter = 15, here we take a look at a FAIL with counter = 16.

The Control signal is held high by the counter during the second half of the total count of 16 (from 0x8 to 0xf).

Note that when Mux-on is high, the mux is open and the Data signal gets captured in the Rx Data flop.

Take a look at the signals in the vicinity of the two vertical dotted lines on the right. The first dotted line aligns with a change in the Data signal which happens when the counter wraps. Since the mux is open (Mux-on is high) the Data is captured by the Rx Data flop on the first receive clock edge following the change in Data. This is marked by the second dotted line and is a Data Stability failure.

Note that, in order to produce a failing trace in this case, the counter needs to wrap around twice. In order to understand why there is no Data Stability failure in the first full count of the counter, take a look at the Grey oval in the waveforms. When the mux is open (when Mux=on is high), note that the Data remains stable and is not changing. Hence there is no Data Stability issue here.

(more…)

CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy