Open side-bar Menu
 Real Talk
Rick Eram, Sales & Marketing VP
Rick Eram, Sales & Marketing VP
Rick has over 20 years of hands on experience in EDA industry, designing tools and directly involved in development and management of engineering teams as well as managing sales and marketing campaigns. Rick's work was instrumental in 2 IPO's with Analogy and Magma. During his tenure at Atrenta he … More »

Value of a Design Tool Needs More Sense Than Dollars

 
June 27th, 2013 by Rick Eram, Sales & Marketing VP

It is interesting when I talk to purchasing managers at semiconductor companies and they use the dollar cost for a tool as the measure of its value.

Tool value can be hard to quantify and a price tag will not tell the whole story. The real cost behind any tool is the engineering effort to use the tool and the real time-saving and efficiency it brings to design teams.

The Meridian CDC solution from Real Intent, for  example, is often compared to tools from other vendors. When technical decision makers are involved, the value is very obvious since they can quantify the difference in effort.

It takes much less time to debug the results. Why? Because Meridian CDC analyzes the complete interface of the crossing and it reports how data and control crossings are associated. This generates dramatically fewer violations for review, despite the fact that all analysis rules are always turned on. Needless to say, having all rules on all the time helps in NOT missing design bugs.

Because of the fast analysis run-time, combined with the low-noise reporting feature of the tool, each iteration for CDC violations is much faster than other tools. As a result the cost of engineering time is much less.

As an example, one of the popular CDC tools generated 130K messages on a design about 10M gates in size. Once the rule set was “optimized” (codeword for watered down) the messages dropped to a mere 20K. Then tinkering with the setup got it down to 8K. Now imagine sitting in front of the screen and trying to go through 8k messages. Don’t forget you may have missed something all together because some rules were turned off to keep the noise down.

So now the designer has to sort through 8K messages, costing productivity, next he has to run it again and wait for results, costing more time. Now if the setup is not right or needs to be further tuned; the process is repeated, and again more waiting for the results and more cost. I think you get the picture. This is not even counting which way the tool may steer you and why using a simple setup may require more fine tuning later on.

Ah, almost forgot! Some of the vendors use a hierarchical analysis as a crutch to help painfully slow algorithms or to manage capacity. So black boxing or “abstract modeling”  are promoted as the solution, which most engineers knows that accuracy is sacrificed and there is a loss of information in a block-level model. Again the risk of missing design bugs because of the inability to analyze CDC bugs at the full chip level, is greater.

So in short, reducing rules to run, or using abstract models is the prescription for added respins and cost, not to mention the risk of having a dead  SOC.

So, The real cost of CDC is not the tool cost but the risk and effort put into the analysis process by using a tool that cannot scale to the necessary complexity of design analysis .

For those who want do a hierarchical analysis without compromises check out the loss-less approach from Real Intent and find out why it gives results that are the state-of-the-art.

Looking at the cost of a tool and comparing it to others might be a fair comparison if the tools are equivalent in performance and usage.  However, the next generation of design analysis tools that have the speed, coverage and targeted debug to handle the most complex SoC designs are invaluable to design teams.  You cannot afford to put up with slow and noisy analysis that can let bugs slip through to tapeout.

Related posts:

Leave a Reply

Your email address will not be published. Required fields are marked *


*

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <strike> <strong>

CST Webinar Series
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy