In Austin, at the 50th DAC earlier this month, I delivered a poster presentation on “Lending a ‘Formal’ Hand to CDC Verification: A Case Study of Non-Intuitive Failure Signatures”. In this second blog in a series, I discuss a set of failures in a common clock domain crossing synchronizer.
The design used for this case study closely mirrors the CDC synchronization scheme shown earlier in Part 1. Two components of the scheme are represented generically in the schematic below. They are
- The logic controlling the loading of the registers in the transmit domain and
- The detection logic on the control signals in the receive domain
A designer can use one of many techniques for implementing the generic components which can be considered as variables for design exploration.
The clock frequencies of the transmit and receive domains, specifically the ratio they imply and the relative reset release of the two clock domains can be considered as the System variables in this experiment.