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Graham Bell
Graham Bell
Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »

Does SoC Sign-off Mean More Than RTL?

May 30th, 2013 by Graham Bell

This blog was first published in the System-Level Design Community of Chip Design Mag.

As the cost of failure continues to rise, SoC engineers see the growing importance of ensuring their work is as correct as possible as soon as possible in the design process. They cannot afford to carry errors forward from one stage to the next, where their impact grows while their causes become more obscured.

This requirement is driving the shift in design exploration and hand-off to the register transfer level. Using RTL for sign-off eases the integration of heterogeneous IP and makes it easier to check that the blocks are interfacing correctly with the host design, easier to check how clocks will cross these interfaces, and easier to check different power signatures and design testability. It also cuts the functional simulation load, especially when designs are being exercised at the system-level by reducing the number of states and the necessity to check for correct functionality.

What tools are available to improve the quality of RTL code before it reaches simulation and passes to synthesis? The latest generation of lint technology can handle full-chip designs of 500 million gates or more, and yet still can offer concise reporting. Timing constraints management and checking ensures correct timing for the block and full-chip level, so long as any changes in the RTL are reflected in the SDC files for the design. The SDC itself needs to be verified for correctness and consistency, and is essential for sign-off-grade analyses such as clock design crossing (CDC).

Reset analysis ensures that the design will come in a known good state, and later iterations of the design can be used to save chip area and routing resources through a more intelligent application of reset signals.

Automatic formal verification techniques can be used to find obscure functional bugs in the RTL, especially in finite state machines, and root out issues such as bus contention or dead code that violate the implicit intent of the RTL.

Clock domain crossing analysis, so important in these days of design reuse, IP, and complex power management schemes, can be carried out using a combination of formal and structural methods, which helps trap the corner case combinations of timing and functionality that lead to errors.

Power analysis and optimization techniques address issues such as reset checking, retention flop and isolation-cell analysis and optimization, clock/power gating, and sequential/combinational optimizations. These interventions can be so extensive that it makes sense to go back to the linting stage to recheck the design, and to clear the way for DFT analysis and optimization.

Working at the RTL signoff level means that even those without DFT expertise can develop DFT strategies and analyze them for the testability they bring to the design.

As a last step, it is important to manage the way that the simulation and synthesis processes handle the unknown (X) states thrown up by power management strategies that turn blocks on and off, and complicates clock-crossing domains. A proper analysis of this issue can reveal functional bugs that have been hidden at the RTL level by too much optimism about the impact of X states, and can reduce the impact of excessive pessimism about the impact of X states after synthesis.

But is RTL signoff also signoff for the SoC? For specific problems such as clock-domain crossing, consistency of SDC, X-propagation issues including reset optimization, and design for testability, the answer is no. Why? Because despite our desire to eliminate gate-level analysis, it is still required to sign off on specific problems. Unfortunately, gate-level analysis severely strains the capacity of EDA tools and processing times are not fast. Only the best-in-class tools can handle both the RTL and gate-level views of the design.

Can legacy RTL tools achieve the desired signoff, or are a new generation of tools needed?

Design teams for years have used a linting-based technology for analysis of designs. When issues are uncovered they are either fixed or waived by the designer. This approach has been used for IP or block-level qualification. We now see attempts to adapt this dated technology for full-chip analysis using an abstraction model for the IP blocks, and then doing a top-level check. This is not a sign-off technology, because the abstraction process blindly omits important details from the block-level. We believe the correct approach is to use a solution that has been architected from the ground up to attack a specific problem domain, and one that uses a smart hierarchical approach that retains block-level information. This will handle both RTL and gate-level views, and will deliver the speed, capacity and precision needed for a sign-off solution.

Real Intent is at booth #1031 at the Design Automation Conference in Austin, TX. Stop by and we would be happy to discuss SoC sign-off with you.

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