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Archive for May 16th, 2013

Be Early to Be Better

Thursday, May 16th, 2013

Intel’s 10-core Westmere Processor

Today’s systems on chip (SoC) are deeply complex in new ways. A dozen or so years ago, a state-of-the-art processor such as the Intel Pentium 4 used 42 million transistors, was built on a 180nm process and relied upon discrete chips to handle its system interfaces. Scroll forward, and the Westmere processor that Intel introduced in 2012 uses 2.6 billion transistors and is built on a 32nm process. The chip includes ten 64bit x86 cores, L3 cache, graphics processing, DDR3 interfaces, virtualisation support and more. This trend to massive integration is even stronger in the mobile space, where SoCs bring together complex computing, communications and entertainment functions on one die.

It’s no longer possible to design all the subsystems of an SoC from scratch and expect to get the chip out in a reasonable timeframe, so today’s SoCs are complex integrations of new logic, IP blocks brought forward from previous designs, and functional and interface IP licensed in from third parties. Some companies are even using third-party IP to build their system interconnect, on the basis of that its communications management support and interfaces to other IP blocks will help get a design out more quickly. In effect, an SoC is a sea of interfaces.


S2C: FPGA Base prototyping- Download white paper

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