Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
Unknown Sign-off and Reset Analysis
May 2nd, 2013 by Graham Bell
Elsewhere, Pranav Ashar, CTO at Real Intent, pointed out that the management of unknowns (X’s) in simulation has become a separate verification concern of signoff proportions. Modern power management schemes affect how designs are reset (start). X management and reset analysis are interrelated because many of the X’s in simulation come from uninitialized flip-flops and, conversely, the pitfalls of X’s in simulation compromise the ability to arrive at a clear understanding of the resetability of a design.
The SystemVerilog standard defines an X as an “unknown” value, which is used to represent when simulation cannot definitely resolve a signal to 1, 0, or Z. Synthesis, on the other hand, defines an X as a “don’t care,” enabling greater flexibility and optimization. Unfortunately, Verilog RTL simulation semantics often mask propagation of an unknown value by converting the unknown to a known, while gate-level simulations show additional X’s that will not exist in real hardware. The result is that bugs get masked in RTL simulation, and while they do show up at the gate level, time consuming iterations between simulation and synthesis are required to debug and resolve them. Resolving differences between gate and RTL simulation results is painful because synthesized logic is less familiar to the user, and X’s make correlation between the two harder. The verification engineer must first figure out whether the X in gate-level simulation is genuine before figuring out whether there is a bug in the design. Unnecessary X-propagation thus proves costly, causes painful debug, and sometimes allows functional bugs to slip through to silicon.
Continued increases in SOC integration and the interaction of blocks in various states of power management are exacerbating the X problem. In simulation, the X value is assigned to all memory elements by default. While hardware resets can be used to initialize registers to known values, resetting every flop or latch is not practical because of routing overhead. For synchronous resets, synthesis tools typically club these with data-path signals, thereby losing the distinction between X-free logic and X-prone logic. This in turn causes unwarranted X-propagation during the reset simulation phase. State-of-the-art low power designs have additional sources of Xs with the additional complexity that they manifest dynamically rather than only during chip power up.
Ascent XV from Real Intent is designed to supplement both the design and the verification phases of development. Optimization is used to ensure complete initialization and reset with minimal hardware. Hazard reports reveal where there is potential for X-Optimism at RTL and X-pessimism at Netlist. X-safe simulation is used to propagate X’s when optimism occurs at RTL and to correct pessimism at the netlist level.
Stuart Sutherland’s “I’m Still In Love With My X! (But, do I Want My X to be an Optimist, a Pessimist, or Eliminated?)” paper at DVCon 2013 was an excellent summary of the good, the bad and the ugly with the appearance of Xs (unknowns) in a design. You see his presentation slides here.
For another perspective on reset optimization and X-propagation and eliminating them in a design take a look at the DVCon poster presentation by MediaTek. I have reproduced it here below. Click on it to get a larger hi-resolution view of the poster.