Vaishnav Gorur, Sr. Applications Engineer
Prior to joining Real Intent, Vaishnav was a logic design engineer at MIPS Technologies where he was responsible for the microarchitecture and RTL Design of the Load-Store Unit and Graduation Unit of the 15-stage out-of-order asymmetric dual-issue superscalar pipeline in the MIPS32® 74K® fully … More »
Conclusion: Clock and Reset Ubiquity – A CDC Perspective
April 4th, 2013 by Vaishnav Gorur, Sr. Applications Engineer
Modern CDC Verification Approaches
Thanks to advances in process technologies and the surging demand for high-performance, low-power, feature-rich consumer devices, the problem of CDC verification and handling of the underlying metastability issues has gone mainstream. Traditional CDC verification using linting, template-based approaches, hacked simulation or static timing approaches have been rendered archaic and are not scalable enough to stand up to the CDC verification challenge. There is an immediate need for a solid CDC verification tool with a robust methodology that not only plays well with the existing tool flow but is flexible enough to accommodate new power optimization flows without compromising on the quality or the extent of coverage.
Real Intent’s Meridian CDC was forged as a CDC tool from the get-go. It has evolved with the design industry, emerged as the market leader in CDC verification and has stood up to CDC verification challenges at major design houses worldwide. The specialized structural and formal analysis engines understand and analyze CDC issues at the grass roots level. They are architected for high-speed and high-capacity, and generate concise low-noise reports that accurately pinpoint CDC issues to enable rapid debugging. The ability of Meridian CDC to run both at the RT level as well as gate-level gives verification teams the wingspan they need to keep designs CDC-clean across the complete design flow.
Meridian’s automatic control-data association is famous in the industry for its ability to encapsulate and present CDC information in an intuitive manner that resonates with users. The extensive checks performed on control and data logic are complemented by checks on ubiquitous clock and reset nets, and make Meridian the consummate tool for CDC sign-off verification from RTL to gates.
 “Utilizing Clock-Gating Efficiency to Reduce Power“, Mitch Dale, Calypto Design Systems, EE Times, Jan. 2008
 “Reducing Power with Advanced Synthesis”, Synopsys Insight, Issue 4, 2011
 “Asynchronous and Synchronous Reset Design Techniques – Part Deux“, Cliff Cummings, Don Mills, Steve Golson, SNUG 2003