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Archive for April, 2013

Automatic RTL Verification: Find Bugs Before Simulation, May 2 Webinar

Thursday, April 25th, 2013
Automatic RTL Verification with Ascent IIV: Find Bugs Before Simulation Real Intent Web-site
  Join us for a Webinar on May 2
   
Real Intent Products
Ascent Implied Intent Verification (IIV) is an early functional verification tool that provides immediate return on investment by quickly finding elusive bugs in RTL blocks. Ascent IIV can improve verification efficiency substantially and detect up to 50% of design functional errors prior to testbench development and simulation. Ascent IIV performs comprehensive verification using automatic check formulation followed by deep-sequential formal analysis.The webinar will introduce tool setup, the kinds of difficult bugs that can be found with the tool, and demonstration of its latest features.
Title: Automatic RTL Verification with Ascent IIV: Find Bugs Simulation Misses
Date: Thursday, May 2, 2013
Time: 10:00 AM – 11:00 AM PDT
After registering you will receive a confirmation email containing information about joining the Webinar.
Space is limited.
Reserve your Webinar seat now at:
https://www2.gotomeeting.com/register/277067418

 

Hear Alexander Graham Bell Speak from the 1880’s

Thursday, April 25th, 2013

A dramatic application of digital technology has allowed researchers to recover Alexander Graham Bell’s voice from a recording held by the Smithsonian—a breakthrough announced for the first time. From the 1880s on, until his death in 1922, Bell gave an extensive collection of laboratory materials to the Smithsonian Institution, where he was a member of the Board of Regents. The donation included more than 400 discs and cylinders Bell used as he tried his hand at recording sound.  Bell today is credited with the invention of the phonograph record which replaced Edison’s cylinder recordings.

Click on the video link below to hear his voice, and read more about the sonic recovery at the Smithsonian Magazine web-site.

Ascent Lint Rule of the Month: NULL_RANGE

Thursday, April 18th, 2013

In recent postings I’ve been writing about the nits and details of the semantics of Verilog, so, in the interest of balance, it’s appropriate to spend some time on VHDL as well.

VHDL has a stronger type system than Verilog, and is rather more explicit in how logic is specified, so you might think that that VHDL is less prone to legal but unintentionally incorrect modeling. It turns out that VHDL has coding gotchas of its own that are different from the ones in Verilog and SystemVerilog.

When you specify a subrange for a type or data declaration, it’s necessary to specify the direction using either ‘to’ or ‘downto’:

signal aa : std_logic_vector(7 downto 0); — descending range, use ‘downto’

signal bb : std_logic_vector(16 to 31); — ascending range, use ‘to’

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System-Level Design Experts At The Table: Verification Strategies – Part Three

Thursday, April 11th, 2013

On February 28, 2013, Ed Sperling, Editor-in-Chief of System-Level Design sat down to discuss verification strategies and changes with Harry Foster, chief verification scientist at Mentor Graphics: Janick Bergeron, verification fellow at Synopsys; Pranav Ashar, CTO at Real Intent; Tom Anderson, vice president of marketing at Breker Verification Systems; and Raik Brinkmann, president and CEO of OneSpin Solutions. Part 3 of the discussion is presented below from the content at http://chipdesignmag.com/sld/blog/2013/03/28/experts-at-the-table-verification-strategies-3/.

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Conclusion: Clock and Reset Ubiquity – A CDC Perspective

Thursday, April 4th, 2013

Modern CDC Verification Approaches

Thanks to advances in process technologies and the surging demand for high-performance, low-power, feature-rich consumer devices, the problem of CDC verification and handling of the underlying metastability issues has gone mainstream. Traditional CDC verification using linting, template-based approaches, hacked simulation or static timing approaches have been rendered archaic and are not scalable enough to stand up to the CDC verification challenge. There is an immediate need for a solid CDC verification tool with a robust methodology that not only plays well with the existing tool flow but is flexible enough to accommodate new power optimization flows without compromising on the quality or the extent of coverage.

Real Intent’s Meridian CDC was forged as a CDC tool from the get-go. It has evolved with the design industry, emerged as the market leader in CDC verification and has stood up to CDC verification challenges at major design houses worldwide. The specialized structural and formal analysis engines understand and analyze CDC issues at the grass roots level. They are architected for high-speed and high-capacity, and generate concise low-noise reports that accurately pinpoint CDC issues to enable rapid debugging. The ability of Meridian CDC to run both at the RT level as well as gate-level gives verification teams the wingspan they need to keep designs CDC-clean across the complete design flow.

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System-Level Design Experts At The Table: Verification Strategies – Part Two

Monday, April 1st, 2013

On February 28, 2013, Ed Sperling, Editor-in-Chief of System-Level Design sat down to discuss verification strategies and changes with Harry Foster, chief verification scientist at Mentor Graphics: Janick Bergeron, verification fellow at Synopsys; Pranav Ashar, CTO at Real Intent; Tom Anderson, vice president of marketing at Breker Verification Systems; and Raik Brinkmann, president and CEO of OneSpin Solutions. Part 2 of the discussion is presented below from the content at http://chipdesignmag.com/sld/blog/2013/03/08/experts-at-the-table-verification-strategies-2/.

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CST Webinar Series



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