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Rick Nordin, VP of Business Development, Breker
Rick Nordin, VP of Business Development, Breker
Rick comes has a 20 year track record in EDA. Prior to joining the Breker team, he served as Marketing Director at Nascentric and at Silicon Design Systems, as Sales Manager for Circuit Semantics, as Methodology Consultant for Cadence, and as District Technical Manager for Synopsys. Rick began his … More »

SoC Verification Can be Cold as Ice

March 28th, 2013 by Rick Nordin, VP of Business Development, Breker

As vice president of business development for Breker Verification Systems, I meet with loads of verification engineers and development teams and always walk away with new insights. Any market analyst who wants help to identify a new or emerging trend in chip design and verification should network with business managers like me. All too often, we’re watching a chip verification shipwreck on par with the sinking of the Titanic, leaving us “Cold as Ice,” as Foreigner intoned in 1977.

You’re cold as ice

You’re willing to sacrifice your chip

This little refrain was playing in my head recently as I was driving away from a painful meeting with a development team working on the verification of a complicated system-on-chip (SoC) design. All was not going well. While the SoC design looked flawless and taped out with no problems, early samples of the chip were not working as expected in some scenarios. The verification engineers weren’t “cold” because they didn’t care; they were close to the iceberg and didn’t realize it.

You never take advice

Someday you’ll pay the price

I know

This team, like so many others, got sucked up in a “stitch and ship” mentality that could sink its corporate ship like an iceberg. While the electronics industry has benefited from reusing blocks of intellectual property (IP), it’s not a panacea. An IP block with a well-defined function can be reused in multiple designs and shared among numerous development teams or companies. All too often, though, development teams assume that because the IP, fabric and memory subsystem have been tested individually, the entire flow will work as intended. After all, if each IP block has been tested and works, it might seem as if the software should be able to stitch them together into a production-worthy device.

I’ve seen it before

It happens all the time

You’re stitching the blocks

You leave the code behind

Without use cases

You’re throwing away

A fortune in mask costs

But someday you’ll pay

Some development teams have lost sight of the need for a full-chip verification strategy and run the risk of multiple failures in the system when used in real-life devices. Other teams recognize the need to do a better job but are prevented from doing do by mandatory tape-out dates or inadequate system-level resources.

SoC designs are architected to have sufficient bus bandwidth to support the required functionality, making performance bugs a reality. Benchmarks need to be run on the SoC to ensure that the expected performance targets are actually met.

Current SoC verification strategies address only the tip of the iceberg, with chunks of verification floes unseen and under water, leaving large holes in system verification coverage. As a result, bugs in SoC silicon are discovered post-silicon during software development and product validation. These late-stage bugs are difficult to find and slow down an already long software validation cycle, increasing time to market and reducing potential revenue. Bugs found by consumers in the field are even worse since they require either hardware replacement or software upgrades with workarounds.

You’re as cold as ice

You’re willing to sacrifice your chip

You want market slice

But someday you’ll pay the price

I know

A solution catching on within development teams is known as graph-based scenario models that capture intended behavior of the IP blocks. These can be combined to create scenario models for major subunits or the complete SoC, where they can automatically generate self-verifying C test cases to run on multiple heterogeneous embedded processors within the SoC. It can verify the complete SoC, providing a level of verification reuse matching that of design reuse and eliminate stitch and ship that will sink the corporate ship every time. And, I’ll drive away from a meeting with the development humming not “Cold as Ice” but rather Buster Poindexter’s “Hot Hot Hot.”

Special thanks to Foreigner for the inspiration. For a look at Foreigner performing their original version watch the YouTube video below.

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