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Archive for March 28th, 2013

SoC Verification Can be Cold as Ice

Thursday, March 28th, 2013

As vice president of business development for Breker Verification Systems, I meet with loads of verification engineers and development teams and always walk away with new insights. Any market analyst who wants help to identify a new or emerging trend in chip design and verification should network with business managers like me. All too often, we’re watching a chip verification shipwreck on par with the sinking of the Titanic, leaving us “Cold as Ice,” as Foreigner intoned in 1977.

You’re cold as ice

You’re willing to sacrifice your chip

This little refrain was playing in my head recently as I was driving away from a painful meeting with a development team working on the verification of a complicated system-on-chip (SoC) design. All was not going well. While the SoC design looked flawless and taped out with no problems, early samples of the chip were not working as expected in some scenarios. The verification engineers weren’t “cold” because they didn’t care; they were close to the iceberg and didn’t realize it.

You never take advice

Someday you’ll pay the price

I know

This team, like so many others, got sucked up in a “stitch and ship” mentality that could sink its corporate ship like an iceberg. While the electronics industry has benefited from reusing blocks of intellectual property (IP), it’s not a panacea. An IP block with a well-defined function can be reused in multiple designs and shared among numerous development teams or companies. All too often, though, development teams assume that because the IP, fabric and memory subsystem have been tested individually, the entire flow will work as intended. After all, if each IP block has been tested and works, it might seem as if the software should be able to stitch them together into a production-worthy device. (more…)

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