Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
The BIG Change in SoC Verification You Don’t Know About
March 21st, 2013 by Graham Bell
Ed Sperling, Editor-in-Chief of System-Level Design recently did a follow-on video interview after his Experts At The Table: Verification Strategies roundtable. Here below, you can read Ed’s introduction to the video interview and the question he posed to Pranav Ashar, CTO at Real Intent. To hear Pranav’s answer, click on the embedded video (which starts at 3:56).
“When you think about the most complex SoCs that are going out the door these days, at 28 and 20nm, it’s a wonder that they still work. A good part of the reason is that they are verified very effectively. Verification traditionally has been 50% to 70% of the NRE that goes into designing these chips and that has not changed. But, the size of the chips and the complexity has grown significantly. So here to discuss what is going on in verification today we have:
… So Pranav, from your perspective what is the big change or big changes that have happened in verification in the past couple of years as we have rising complexity in a chip?”