Open side-bar Menu
 Real Talk
Vaishnav Gorur, Sr. Applications Engineer
Vaishnav Gorur, Sr. Applications Engineer
Prior to joining Real Intent, Vaishnav was a logic design engineer at MIPS Technologies where he was responsible for the microarchitecture and RTL Design of the Load-Store Unit and Graduation Unit of the 15-stage out-of-order asymmetric dual-issue superscalar pipeline in the MIPS32® 74K® fully … More »

Part Six: Clock and Reset Ubiquity – A CDC Perspective

 
March 21st, 2013 by Vaishnav Gorur, Sr. Applications Engineer

C. The need for reset signals to be asynchronously asserted and synchronously de-asserted.

Although it appears that use of asynchronous resets is preferred due to the ability to reset a subsystem without an active clock edge, there is still a catch. Asynchronous resets are, by definition, asynchronous both during assertion and de-assertion of reset. The assertion, as discussed earlier, does not pose an issue as it is independent of the clock signal. However, the de-assertion is still subject to meeting reset recovery times. The reset recovery time is similar to a setup timing condition on a flip-flop; it defines the minimum amount of time between the de-assertion of reset and the next active clock edge.

Figure 9. Waveforms depicting reset recovery time

If the asynchronous reset is de-asserted near the active edge of the clock and violates the reset recovery time, it could cause the flip-flop to go metastable, resulting in potential loss of the reset value of the flip-flop. A non-deterministic reset value defeats the whole purpose of using a resettable flip-flop. Hence, a fully asynchronous reset is also not a viable reset solution for systems with multiple clock domains.

As described above, synchronous resets have issues during reset assertion and asynchronous resets have issues during reset de-assertion. To overcome these obstacles, an ideal solution is to combine the best of both worlds: use a scheme that involves asynchronous assertion yet synchronous de-assertion of reset.

Figure 10. Reset synchronizer

In Figure 10, the main reset signal entering the subsystem asynchronously resets the two flip-flops forming the reset synchronizer. This reset synchronizer then drives the asynchronous reset signal for the rest of the subsystem ensuring that all the flip-flops in the subsystem are asynchronously reset. Note that this reset assertion is asynchronous to the subsystem clock, which need not be active at the time of reset. When the main reset signal de-asserts, it takes two active clock edges for the subsystem flip-flops to be taken out of reset. Since this reset removal is governed by the active clock edge, the reset de-assertion is synchronous.

Figure 11. Flip-flops reset by a signal from an asynchronous clock domain

Use of reset synchronizer schemes to asynchronously reset subsystems is a robust and reliable solution to the reset distribution problem. Meridian CDC identifies situations where such schemes can be employed to protect against subtle metastability issues in the reset architecture. For example, in Figure 11, the flip-flops in clock domain B would be identified by Meridian CDC as being asynchronously reset from clock domain A without the use of a reset synchronizer.

 

*** Next time we will cover Modern CDC Verification Methods ***

Related posts:

Leave a Reply

Your email address will not be published. Required fields are marked *


*

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <strike> <strong>

CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy