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Archive for March 21st, 2013

Part Six: Clock and Reset Ubiquity – A CDC Perspective

Thursday, March 21st, 2013

C. The need for reset signals to be asynchronously asserted and synchronously de-asserted.

Although it appears that use of asynchronous resets is preferred due to the ability to reset a subsystem without an active clock edge, there is still a catch. Asynchronous resets are, by definition, asynchronous both during assertion and de-assertion of reset. The assertion, as discussed earlier, does not pose an issue as it is independent of the clock signal. However, the de-assertion is still subject to meeting reset recovery times. The reset recovery time is similar to a setup timing condition on a flip-flop; it defines the minimum amount of time between the de-assertion of reset and the next active clock edge.

Figure 9. Waveforms depicting reset recovery time

If the asynchronous reset is de-asserted near the active edge of the clock and violates the reset recovery time, it could cause the flip-flop to go metastable, resulting in potential loss of the reset value of the flip-flop. A non-deterministic reset value defeats the whole purpose of using a resettable flip-flop. Hence, a fully asynchronous reset is also not a viable reset solution for systems with multiple clock domains.

As described above, synchronous resets have issues during reset assertion and asynchronous resets have issues during reset de-assertion. To overcome these obstacles, an ideal solution is to combine the best of both worlds: use a scheme that involves asynchronous assertion yet synchronous de-assertion of reset. (more…)

The BIG Change in SoC Verification You Don’t Know About

Thursday, March 21st, 2013

Ed Sperling, Editor-in-Chief of System-Level Design recently did a follow-on video interview after his Experts At The Table: Verification Strategies roundtable.  Here below, you can read Ed’s introduction to the video interview and the question he posed to Pranav Ashar, CTO at Real Intent.  To hear Pranav’s answer, click on the embedded video (which starts at 3:56).

“When you think about the most complex SoCs that are going out the door these days, at 28 and 20nm, it’s a wonder that they still work.  A good part of the reason is that they are verified very effectively.  Verification traditionally has been 50% to 70% of the NRE that goes into designing these chips and that has not changed.  But, the size of the chips and the complexity has grown significantly.  So here to discuss what is going on in verification today we have:

  • Janick Bergeron, verification fellow at Synopsys
  • Harry Foster, chief verification scientist at Mentor Graphics
  • Pranav Ashar, chief technology officer at Real Intent
  • Rai Brinkmann, president and CEO of OneSpin Solutions
  • Tom Anderson, vice president of marketing at Breker Verification Systems

So Pranav, from your perspective what is the big change or big changes that have happened in verification in the past couple of years as we have rising complexity in a chip?” (more…)

S2C: FPGA Base prototyping- Download white paper

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