Open side-bar Menu
 Real Talk

Archive for March 14th, 2013

Ascent Lint Rule of the Month: COMBO_NBA

Thursday, March 14th, 2013

One of the first things you learn about when modeling logic in Verilog is to avoid race conditions.  You can do this by coding clocked registers with non-blocking assignments. So why not make life simple, and use non-blocking assignments for combinational logic too?

Let’s back up a bit and review the basics:
A problem occurs when the target of one register assignment feeds into the assignment for the next register stage. Without some kind of delay, a value could ‘race’ from one assignment right through the next register stage in the same instant of simulation time.

always @(posedge clk)

bb = f1(aa);  // When clk rises, bb is determined by aa

always @(posedge clk)

cc = f2(bb);  // The same instant, cc could get the new result.. This is not what we want! (more…)

System-Level Design Experts At The Table: Verification Strategies – Part One

Thursday, March 14th, 2013

On February 28, 2013, Ed Sperling, Editor-in-Chief of System-Level Design sat down to discuss verification strategies and changes with Harry Foster, chief verification scientist at Mentor Graphics; Janick Bergeron, verification fellow at Synopsys; Pranav Ashar, CTO at Real Intent; Tom Anderson, vice president of marketing at Breker Verification Systems; and Raik Brinkmann, president and CEO of OneSpin Solutions. Part 1 of the discussion is presented below from the content at


CST Webinar Series
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy