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Vaishnav Gorur, Sr. Applications Engineer
Vaishnav Gorur, Sr. Applications Engineer
Prior to joining Real Intent, Vaishnav was a logic design engineer at MIPS Technologies where he was responsible for the microarchitecture and RTL Design of the Load-Store Unit and Graduation Unit of the 15-stage out-of-order asymmetric dual-issue superscalar pipeline in the MIPS32® 74K® fully … More »

Part Five: Clock and Reset Ubiquity – A CDC Perspective

March 7th, 2013 by Vaishnav Gorur, Sr. Applications Engineer

An asynchronous reset control that crossed clock domains but was not synchronously de-asserted, causing a glitch in control lines to an FSM.

The scenario above is at the confluence of the following three design requirements, and resulted in a failure when one of them was not met:

A. The need for multiple clock domains in the design that can be independently reset.
B. The need to use flip-flops that are asynchronously reset.
C. The need for reset signals to be asynchronously asserted but synchronously de-asserted.

Let us delve deeper into each of these design requirements in order to understand the context of the failure.

A. Need for multiple clock domains in the design that can be independently reset.

In the event of failure, a hardware reset is a necessity to restore the system to a known initial state from which it can start functioning deterministically. Power-cycling a modem is a classic example of allowing enough time for a system reset to propagate to all sub-systems, some of which might be operating at different clock frequencies. From a verification standpoint, since each of these subsystems typically is designed and verified separately, the presence of a reset in each subsystem enables effective block-level verification by ensuring that the design is in a known state for simulation.

It is good design practice for every flip-flop in a design to be resettable. In order to extract higher performance in functional mode, there may be certain parts of the design (e.g. pipeline registers) which themselves are not resettable but whose upstream registers are. In such cases, the design takes more clock cycles to be put into a known state as the upstream reset values need to propagate down to these registers. Often, this is an acceptable tradeoff but one that the system designers need to be cognizant of when determining the reset strategy for the SoC.

Several benefits stem from the ability to independently reset subsystems, some of which are:

  1. Managing functional complexity of the system
  2. Avoiding the long latency of a system-wide reset in the event of a subsystem failure
  3. Being able to run simulations on a subsystem level prior to integration

B . The need to use flip-flops that are asynchronously reset.

Having established the need for and the utility of multiple resettable clock domains in an SoC, the question of which type of reset to use (synchronous or asynchronous) arises.

By definition, a synchronous reset is one in which the reset occurs during the active edge of the clock feeding the flip-flop. Since the reset signal is timed, the flip-flop is immune to glitches occurring away from the active clock edge. Such glitches that occur on the reset line or in the combinational logic feeding the synchronous reset do not affect the flip-flop as the reset is only sampled at the clock edge.

Figure 7. Usage of synchronous reset with
combinational logic feeding the D input of the flip-flop

However, the requirement for a synchronous reset to have an active clock turns out to be a double-edged sword. As mentioned earlier, SoC designs are being architected for reduced power consumption. One of the primary ways this is achieved is by turning off clock and power domains when they are unused.

Turning off the clock to a subsystem violates the premise on which usage of a synchronous reset is based: that the clock to the flip-flop being reset is active. For this reason, only an asynchronous reset will work since it does not require the presence of an active clock edge during reset assertion.

Figure 8. Use of asynchronous reset and its non-involvement with combinational logic feeding the D input of the flip-flop

Asynchronous resets are incorporated into flip-flops via a reset pin and do not need an active edge of the clock for reset assertion. If the polarity of the reset signal is active-low, the flip-flop gets the reset value when the reset signal is de-asserted.

Note that, unlike synchronous resets, asynchronous resets are not involved in the logic feeding the ‘D’ pin and hence do not factor into the single-cycle timing of the datapath. This allows designers to tune the datapath without having to worry about factoring in the delays from the reset-related logic.

Consequently, a system with multiple clock domains requires the use of asynchronously reset flip-flops to:

  1. Have the ability to reset flip-flops to a known value AND
  2. Be able to do so without the clock to those domains being active.

*** Next time we will look at Part C. The need for reset signals to be asynchronously asserted but synchronously de-asserted. ***

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