Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
Quick DVCon Recap: Exhibit, Panel, Tutorial and Wally’s Keynote
February 28th, 2013 by Graham Bell
We just finished a BUSY week of activity at the Design and Verification Conference. The exhibits were open for 3 hours on Tues. and Wed. in the late afternoon. The floor was buzzing when the technical program was done for the day and the beverage bar helped to fuel everyone’s spirits. I think floor traffic may have been lighter than earlier years, but the floor layout was definitely more conducive for people to move around.
Real Intent sponsored a panel, “Where Does Design End and Verification Begin?”, which had over 140 attendees listen to experts from ARM, Mentor Graphics, Intel, GarySmithEDA, and Real Intent. The discussion was lively and the moderator, Brian Hunter from Cavium, threw at least one gibe. I knew it was a very good panel when attendees were echoing the discussion at another panel later that day. I had my video camera recording the back-and-forth and will be posting clips from the panel in the weeks ahead on this blog.
Real Intent along with Calypto and DeFacTo sponsored a Tutorial on Thursday afternoon on “Pre-Simulation Verification for RTL Sign-off.” The actual audience was less than the approximately 85 that had registered, but were actively listening with many questions as we covered the topics of DFT, ESL, Power optimization, lint, automatic functional simulation, X-verification and optimization, SDC management and verification, and finally clock domain crossing verification and sign-off. A lot of material to cover in 3 hours, but we delivered the goods and audience members stayed to ask more question when the presentation was done.
One highlight of the event was Wally Rhine’s (Mentor CEO) keynote speech. While I was not able to attend, I did hear about one slide showing a graph with a curve dropping dramatically from 100 down to 2. The graph was not labeled, so the audience was looking for an explanation from Wally. With a big smile he said “This is number of companies left in the marketplace for Synopsys to acquire.” The audience enjoyed a good laugh.
Another highlight from Wally’s talk was his comments on how we have moved away from PhD-expert formal verification to “push button formal.” He then went on to describe those push button offerings he sees across the industry. First was clock domain crossing (CDC), followed by automatic functional verification (e.g. discovering dead code, or deadlocks in finite-state machines), and lastly analysis of how ‘Xs’ (unknowns) are propagated in a design (which is a common reset issue that needs analysis).
Wally’s final slide concluded that with the acceleration of innovation in design, the macro enablers for verification success include multi-engine verification platforms and application-specific formal. This is in complete alignment with the Ascent and Meridian products Real Intent offers to designers and verification engineers. Not only is Wally Rhines a great keynote speaker. He is also right.
For a more detailed look at Wally’s keynote, check out my blog post on System Level Design.