Vaishnav Gorur, Sr. Applications Engineer
Prior to joining Real Intent, Vaishnav was a logic design engineer at MIPS Technologies where he was responsible for the microarchitecture and RTL Design of the Load-Store Unit and Graduation Unit of the 15-stage out-of-order asymmetric dual-issue superscalar pipeline in the MIPS32® 74K® fully … More »
Part Four: Clock and Reset Ubiquity – A CDC Perspective
February 21st, 2013 by Vaishnav Gorur, Sr. Applications Engineer
Sequential clock gating is a relatively newer, more complicated technique that involves the identification of enable signals based on analysis that spans multiple clock cycles. By examining the design across sequential boundaries, advanced power optimization tools can identify data dependencies, observable don’t care conditions and unused states. Based on this information, they then formulate enable conditions to shut off the clock to groups of flip-flops in the design. Sequential clock gating typically provides higher power savings compared to its combinational counterpart as it has the potential to turn off more registers for a larger number of clock cycles.
A practical example of a sequential clock gating scheme is to turn off subsequent banks of pipeline registers based on the propagated value of the enable signal in the current pipeline stage. This concept can be boiled down further and restricted to a single flop.
Note that it is possible to gate the clock to a flop based on the output of the flop in the previous cycle and the incoming data value. A simple XOR of the output and incoming input signal can be used as the enable signal for the clock gater as depicted in Figure 5. This technique is employed in power optimization tools.
Recall the combinational clock gating example where a synthesis tool that was not CDC-aware inferred clock gating logic susceptible to metastability. A similar situation can arise with a power optimization tool. Consider the simple example shown in Figure 6 where a control signal is properly synchronized with a dual-flop synchronizer. An automated power optimization tool that is not CDC-aware might not recognize the synchronization mechanism and insert clock gaters on individual flops of the synchronizer as shown.
CDC design guidelines dictate that the output of the first flop of a synchronizer is susceptible to metastability and that it not be used functionally. The transformation introduced by the power optimization tool violates this dictum by using the output of the first flop of the synchronizer to derive the enabling condition for the clock gater. This can cause non-deterministic operation of the clock gater, leading to potentially spurious control signal values propagating downstream resulting in functional control flow failures. Again, a logical equivalence checking tool will not catch issues of this nature.
Real Intent’s Meridian CDC runs a substantial suite of thorough checks on clocks, derived clocks and gated clocks. It pinpoints clock gating issues such as glitches, unsafe CDC practices, non-deterministic clock states and incorrect clock gating techniques. It protects against unintentional yet catastrophic side-effects caused by synthesis and power optimization tools.
*** Next time we will look at an asynchronous reset control that crossed clock domains but was not synchronously de-asserted, causing a glitch in control lines to an FSM. ***