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Archive for February, 2013

Quick DVCon Recap: Exhibit, Panel, Tutorial and Wally’s Keynote

Thursday, February 28th, 2013

We just finished a BUSY week of activity at the Design and Verification Conference.  The exhibits were open for 3 hours on Tues. and Wed. in the late afternoon.  The floor was buzzing when the technical program was done for the day and the beverage bar helped to fuel everyone’s spirits.  I think floor traffic may have been lighter than earlier years, but the floor layout was definitely more conducive for people to move around.

Vaishnav Gorur, Sr. Field Applications Engineer, at the Real Intent DVCon 2013 booth

Real Intent sponsored a panel, “Where Does Design End and Verification Begin?”, which had over 140 attendees listen to experts from ARM, Mentor Graphics, Intel, GarySmithEDA, and Real Intent.   The discussion was lively and the moderator, Brian Hunter from Cavium, threw at least one gibe.  I knew it was a very good panel when attendees were echoing the discussion at another panel later that day.  I had my video camera recording the back-and-forth and will be posting clips from the panel in the weeks ahead on this blog. (more…)

Part Four: Clock and Reset Ubiquity – A CDC Perspective

Thursday, February 21st, 2013

Sequential clock gating is a relatively newer, more complicated technique that involves the identification of enable signals based on analysis that spans multiple clock cycles. By examining the design across sequential boundaries, advanced power optimization tools can identify data dependencies, observable don’t care conditions and unused states. Based on this information, they then formulate enable conditions to shut off the clock to groups of flip-flops in the design. Sequential clock gating typically provides higher power savings compared to its combinational counterpart as it has the potential to turn off more registers for a larger number of clock cycles.

Figure 5. XOR self-gating

A practical example of a sequential clock gating scheme is to turn off subsequent banks of pipeline registers based on the propagated value of the enable signal in the current pipeline stage. This concept can be boiled down further and restricted to a single flop.

Note that it is possible to gate the clock to a flop based on the output of the flop in the previous cycle and the incoming data value. A simple XOR of the output and incoming input signal can be used as the enable signal for the clock gater as depicted in Figure 5.  This technique is employed in power optimization tools. (more…)

Does Extreme Performance Mean Hard-to-Use?

Thursday, February 14th, 2013

I must admit that I am having a blast seeing all the Field reports that mention prospective customers’ impressions of Real Intent’s Ascent Lint product— three in just the past week. The typical comment is that it “easy to use and intuitive.”  As we built Ascent Lint from the ground up three years ago, usability was kept in mind starting from day one.

When deciding on both the command and the graphical user interface, I take the perspective of a user who has never used our tool before and doesn’t want to learn a new tool environment.  I pretend I want to have everything at my fingertips, just like royalty.  On the Ascent Lint engineering team, we think ahead of all the “what-if” debug scenarios so the end-user can focus on their design and fix actual problems.

The user interface is just one factor contributing to Ascent Lint being “easy to use”.  Its next generation engine delivers the highest performance and the highest capacity available in the market.  No other tool has been able to beat the speed and capacity of Ascent Lint which is up to 50X faster than other products.  It delivers an almost unbelievable runtime of less than an hour for a 450 million gate design run from chip level flat.

What does that mean in terms of usability?  Well, it means the user does NOT need to learn a new flow for next generation designs that are of hundreds of million gates.  They are free from writing complex multi-iteration hierarchical scripts to get around the limitations in tools that cannot support these designs.  It avoids the need to run multiple lint jobs at different levels of the hierarchy and eliminates the added noise that is always present when merging multiple analysis reports into a single one.  The raw performance and capacity advantages of Ascent Lint lead to significant process simplification and reduction in cost, time and resources. (more…)

Part Three: Clock and Reset Ubiquity – A CDC Perspective

Wednesday, February 13th, 2013

Combinational clock gating is a relatively straightforward technique of disabling the clock to registers when the register output does not change. This involves identifying combinational logic conditions that cause a register to hold its previous value and using it as an enable signal for the clock pin instead.

Figure 3. Combinational clock gating

Opportunities to insert combinational clock gating can be identified by power-aware RTL synthesis tools based on the analysis of the combinational cone of logic between registers. Figure 3 illustrates a transformation involved in combinational clock gating. Once the clock gating insertion is complete, a logical equivalence checking tool is employed to ensure that the resulting design with clock gates inserted is indeed functionally equivalent to the original design. The synthesis tool, however, is not clock domain crossing aware and might perform optimizations that violate CDC principles at the boundary interfaces between clock domains. Consider the following situation where the two clocks clkA and clkB are asynchronous.


Ascent Lint Rule of the Month: ARITH_CONTEXT

Thursday, February 7th, 2013

Quick, what’s two plus two? The answer is four, of course, assuming you have enough bits to compute the entire result. When writing code in Verilog, this is not always a safe assumption.

In Verilog, each expression is determined to have a specific bit length. For the logic expressions (e.g. and, or, xor) and arithmetic expressions (e.g. add, subtract, multiply), if the expression is on the right-hand-side of an assignment, then the length is determined by the size of the result on the left-hand-side. If the expression isn’t in an assignment, or appears in a concatenate or index range, then its length is determined by its largest argument. Literal integers, specified without a length, are 32 bits long.

For example, in the assignment:

 qq[2:0] = aa[1:0] + bb[1:0]

The assignment is to a three-bit value, so the add operation of aa and bb is determined to be three bits wide. But in the statement:

 $display(“This value is %x”, mem[ aa[1:0] + bb[1:0] ]);

the add operation here is two bits long, as it’s largest operand is two bits. If aa and bb are both 2’d2, then the carry bit is discarded and the result of the add here is 2’d0. (The details of how expression lengths are determined are spelled out in the Verilog Language Reference Manual, IEEE-1364.)


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