Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
“Where Does Design End and Verification Begin?” and DVCon Tutorial on Static Verification
January 31st, 2013 by Graham Bell
Besides our usual exhibit at the Design and Verification Conference in San Jose at the end of February, Real Intent has organized a Panel and a ½ day Tutorial which I think highlights some of the changes happening in our industry, and that may have been overlooked.
The Panel discusses the interesting topic “Where Does Design End and Verification Begin?” The abstract states that design and verification are “joined at the hip” as the initial spec for simulation and architectural exploration leads to an RTL model and finally a gate-level implementation. It claims that the verification flow applies assertions, testbenches, timing constraints and automation methods as the design devolves. Are they completely entwined? From what I have seen, design teams typically see a boundary between those that write the RTL code and those that verify it. Is there a clean hand-off between D and V? And what is the best practice for the industry? I look forward to hearing what the moderator, Brian Hunter of Cavium Networks and the panelists John Goodenough (ARM), Oren Katzir (Intel), Harry Foster (Mentor), Pranav Ashar (Real Intent) and Gary Smith (GSEDA) will say about these questions on the morning of Wed. Feb. 27.
Secondly, the ½ day Tutorial on “Pre-Simulation Verification for RTL Sign-off” presents the toolset that surrounds the traditional dynamic simulation and timing analysis used by engineers. The integration of heterogeneous IP and design units into an SOC require confirmation of protocols, power budgets, testability and the correct operation of multiple interfaces and clock domain crossings (CDC). Simulation can theoretically be used to fully test an SOC but the cost of complete RTL testing is beyond what design teams can afford. To reduce cost and the risk of missing critical tests, abstract modeling and pre-simulation static analysis of RTL have become imperative in SOC design flows.
The presentations will cover power exploration, analysis and optimization using an abstract model with high-level synthesis (HLS), followed by the RTL static verification for: syntax and semantic checking (lint); constraints planning and management; reset analysis and optimization; automatic intent verification; CDC sign-off; DFT analysis and insertion; and X-analysis and optimism/pessimism correction. Each step represents a substantial hardening of the design and is best served by a top-of-the-line tool designed specifically for that step.
The following elements will be presented:
Bryan Bowyer, Sr. Design Specialist, Calypto Design Systems
Bryan Bowyer is a leading expert in designing with high-level synthesis(HLS), with over 12 years experience both designing and using HLS tools. Bryan has created a wide range of hardware using HLS, from FFTs to AXI Interfaces in C++ and SystemC. Bryan is currently leading the Product Design team at Calypto Design Systems, and is responsible for HLS, formal equivalence and power optimization.
Chouki Aktouf, President and CEO, DeFacTo Technologies
Prior to founding DeFacTo, Dr. Aktouf was an associate professor of Computer Science at the University of Grenoble 2 and leader of the dependability research group within the INPG (Institut National Polytechnique de Grenoble), where more than 18 man-years of work were applied to what is now DeFacTo’s unique approach to design for test (DFT). He holds a PhD in Electric Engineering from INPG (France) and did post-doctoral research in the electrical engineering department at University of Southern California in Los Angeles and Dalhousie University in Canada. A member of the IEEE and TTTC, Dr. Aktouf has more than 15 years experience in design and test and in fault-tolerance. As well as leading several international research projects in the USA (DARPA), Canada (NSERC) and Europe, he has published more than 150 scientific publications in international conferences, periodicals, magazines and several book chapters.
Pranav Ashar, CTO, Real Intent
Dr. Pranav Ashar brings two decades of EDA expertise to Real Intent. Pranav received his M.S. and Ph.D. in EECS with emphasis on EDA from the University of California, Berkeley in 1989 and 1991, respectively. He then joined NEC Labs in Princeton, NJ where he developed a number of EDA technologies that have influenced the industry. Pranav has authored about 70 publications in refereed conferences and journals with approximately 800 citations, and co-authored a book titled “Sequential Logic Synthesis”. He has 35 patents granted and pending, many of which have been licensed or part of business enablement. Pranav was an adjunct faculty in the CSEE department at Columbia University where he has taught graduate and undergraduate courses on VLSI design automation, VLSI Verification, and VLSI design.
The cost for the tutorial is $85 unless you choose one of the conference registration packages that include the tutorial. Attendees will get cool giveaways from each of the presenting companies.
I look forward to hearing back from the SLD readership on what they thought of the Panel and the ½ day Tutorial. See you at the show!