Besides our usual exhibit at the Design and Verification Conference in San Jose at the end of February, Real Intent has organized a Panel and a ½ day Tutorial which I think highlights some of the changes happening in our industry, and that may have been overlooked.
The Panel discusses the interesting topic “Where Does Design End and Verification Begin?” The abstract states that design and verification are “joined at the hip” as the initial spec for simulation and architectural exploration leads to an RTL model and finally a gate-level implementation. It claims that the verification flow applies assertions, testbenches, timing constraints and automation methods as the design devolves. Are they completely entwined? From what I have seen, design teams typically see a boundary between those that write the RTL code and those that verify it. Is there a clean hand-off between D and V? And what is the best practice for the industry? I look forward to hearing what the moderator, Brian Hunter of Cavium Networks and the panelists John Goodenough (ARM), Oren Katzir (Intel), Harry Foster (Mentor), Pranav Ashar (Real Intent) and Gary Smith (GSEDA) will say about these questions on the morning of Wed. Feb. 27.
Secondly, the ½ day Tutorial on “Pre-Simulation Verification for RTL Sign-off” presents the toolset that surrounds the traditional dynamic simulation and timing analysis used by engineers. The integration of heterogeneous IP and design units into an SOC require confirmation of protocols, power budgets, testability and the correct operation of multiple interfaces and clock domain crossings (CDC). Simulation can theoretically be used to fully test an SOC but the cost of complete RTL testing is beyond what design teams can afford. To reduce cost and the risk of missing critical tests, abstract modeling and pre-simulation static analysis of RTL have become imperative in SOC design flows.