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Vaishnav Gorur, Sr. Applications Engineer
Vaishnav Gorur, Sr. Applications Engineer
Prior to joining Real Intent, Vaishnav was a logic design engineer at MIPS Technologies where he was responsible for the microarchitecture and RTL Design of the Load-Store Unit and Graduation Unit of the 15-stage out-of-order asymmetric dual-issue superscalar pipeline in the MIPS32® 74K® fully … More »

Part Two: Clock and Reset Ubiquity – A CDC Perspective

January 24th, 2013 by Vaishnav Gorur, Sr. Applications Engineer

The Evolution of Clocks and Resets

Traditional clock and reset mechanisms typically were based on a master clock and reset distributed throughout the chip. Today, the die size is large enough that it is impractical to distribute the same fast clock to all parts. In addition, power management dictates that there be multiple VDD and clock domains on the chip that can be turned on and off independently. Clock frequencies in communicating domains (asynchronous or not) can differ by an order of magnitude and clock frequencies are allowed to vary dynamically based on throughput requirements or for power optimization. The proliferation of gated clocks for power optimization has introduced new tools in the design flow. The process of adding clock gates traditionally done by logic designers is now being automated to ensure that no power savings are left on the table. The premise for usage of gated clocks is that there is no modification of the original functionality. Logical equivalence checking tools need to be employed in the design flow to ensure this is indeed the case.

The large amount of clock gating, the variety of clock gating techniques, the nontrivial control circuitry involved and the likelihood that most of it is automatically inserted by a synthesis tool or power optimization tool further complicates verification. The implementation of power-up reset is also more complex today as it is designed to optimize power and physical layout. It is imperative that clock and reset schemes be comprehensively verified prior to analysis of the rest of the design. Empirical evidence suggests that a lot of issues initially diagnosed as being control or datapath-related are eventually traced to improper clock and reset behavior.

Exacerbating the verification problem is the fact that synthesis and power optimization tools are not glitch-aware and that there exists a distinct possibility that glitch-susceptible logic is inserted during optimization phases. This suggests that verification tools for clock and reset analysis be operable at the RT level as well as at the gate level. The following section details some real-life examples of the issues mentioned.

Silicon re-spins caused by clock and reset-related failures

Several companies have experienced painful silicon re-spins as a result of not comprehensively verifying clock and reset-related CDC issues. The ones described below are quite revealing:

Example I: Gating logic automatically inserted by back-end tools for power management, resulting in glitches on a clock.

The scenario above was created due to the adoption of automated methods for power optimization and remained undetected owing to the lack of sufficient verification efforts to analyze the side-effects of the achieved power reduction. It is important to understand why design methodologies are driven to adopt automated power optimization tools prior to analyzing the pitfalls that accompany the usage of such tools.

Of the three design optimization criteria– Performance, Power and Area (PPA), power consumption clearly is a runaway first nowadays. The uptick in demand for smartphones and mobile devices coupled with the plethora of demanding software applications they run means that every mV of battery power needs to be used judiciously. At the SoC level, this translates to having the ability to dynamically turn off parts of the chip that are not being used. If the granularity is dialed down to the RT level, we enter the territory of clock gating- a technique where the clock net to sequential state elements is intelligently turned off based on the usage of those state elements in the design. The clock distribution network is the single largest source of dynamic power consumption. Not toggling the clock net during inactive periods results in significant power savings. Additionally, turning off the switching activity in the flip-flops reduces the internal power consumed by the state elements.

Given the magnitude and complexity of today’s designs, it is in the best interest of designers to leverage automated tools that identify power saving potential and insert appropriate clock gating mechanisms in the RTL without affecting the functionality of the design. This enables them to maximize power savings not only in blocks they own, but also in legacy blocks of code that are constantly leveraged in next-generation designs of a product line. The fact that only 20% or less of a next-gen design is built from scratch is reason enough to look for power savings in legacy designs. Having understood the need for automated power optimization tools and their role in the design flow, lets take a look at how these technologies can trip designs up in the seemingly orthogonal space of clock domain crossing analysis. The following sections depict issues with both types of clock gating insertion that automated power optimization tools perform – combinational and sequential clock gating.

*** Next time we will look at Combinational Clock Gating ***

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