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Archive for January 3rd, 2013

Predictions for 2014, Hier. vs Flat, Clocks and Bugs

Thursday, January 3rd, 2013

Happy New Year! In this first blog post of 2013, I am relaying some thoughts and opinions that have come out over the last month from Real Intent.

Prakash Narain, President and CEO, at Real Intent was asked in the Dec. 2012 issue of System Level Design (SLD) what he saw as the big issues and developments in design over the next 12 to 24 months. Here is his answer:

“On-chip complexity will see a major jump in the next silicon node. The 20nm node may have 14nm transistors, or semi companies may skip 20nm and go straight to 14nm. Either way, there will be significantly more transistors in the next node than in the typical transition. Impact will be felt on EDA tools across the board. The largest impact will be on verification tools that don’t have the luxury of a sliding scale of Quality-of-Result (QoR).  Today, we are seeing 450M gate SoC designs for Clock Domain Crossing (CDC) verification. With the new nodes and the demand for ever-greater feature sets and performance by consumers, 1G-gate designs will be the top end in 12 to 24 months. The challenge will be to scale verification tools to handle these designs and give signoff-accurate results in hours and not days or weeks.”

Dr. Pranav Ashar, CTO at Real Intent gave his thoughts to Ed Sperling of SLD in his Adventures In Verification story on the how both hierarchical and flat methodologies play a role in SoC verification.  He believes a marriage of both approaches is the best.  Here is a short excerpt from the story concerning this issue: (more…)

DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers



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