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Graham Bell
Graham Bell
Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »

Real Intent Reports on DVClub Event at Microprocessor Test and Verification Workshop 2012

December 13th, 2012 by Graham Bell

I had the pleasure of attending the luncheon organized by the Design Verification Club of Austin on the mystical date 12/12/12.  It was the concluding event at the Microprocessor Test and Verification Workshop which is held every year at this time.  DVClub lunch-time talks are designed to share knowledge among the verification community and happen several times per year. Real Intent is a new sponsor for DVClub and we join sponsors such as Cadence, Oracle and Breker.

Eric Hennenhoefer, Director of Verification Enablement at ARM, who is a founder and organizer for DVClub generously participated in a video interview which can be seen below.  I think these events are a good idea and look forward to sponsoring the next one in Silicon Valley at Dave & Busters in Milpitas on Feb. 7.  The talk will be given by Dean Drako, CEO & President, IC Manage.

At the Austin event, Zihno Jusufovic from AMD spoke on “Processor Verification of AMD’s  ‘Jaguar': A next generation low power x86 core.”  While Zihno declined to speak on camera about his talk (something about review by pesky lawyers), I was able to glean a few points.  Zhino led what he described as a small verification team and they needed to use several strategies to use their resources efficiently.   Here is what I learned:

  • ‘Jaguar’ is the next-generation low-power core that follows ‘Bobcat’
  • There is a cluster of up to 4 cores all sharing access to a cluster of L2 memory caches
  • Since the verification team was small, much of the test plan involved use of directed random test-benches which are much easier to maintain as the design develops
  • Not all the blocks for a core were signed-off before intergration and were debugged at the core-level
  • 1/3 of the tracked bugs were fixed at the block-level, 2/3 at the core-level and 4% at the SOC-level
  • To keep the verification on track, a ready-to-implement strategy was taken where a minimum of 90% of the design code needed to pass each and every time.  If it fell below that line, remedies were immediately implemented
  • Zhino and his team liked to give the design team specific hints as to what they thought was the cause of a problem and where the fix should be applied.  This required an intimate knowledge of the design which may not be typical for other design teams who might throw the bugs “over the wall” for the design team to fix.
  • There was some testbench re-use from Bobcat that often was in OVM (SystemVerilog) style with a trend to use UVM testbenches.
  • The verification of the interaction of the various power modes for the cluster of CPUs in Jaguar was described as extremely complex (e.g., each core can wake up or go to sleep on its own, and may need to immediately wake up after being told to go to sleep; if all cores are asleep, other power-saving modes get activated for the bus interfaces, and so on).
  • A new methodology was developed to verify all the different possible power modes.

Here is the interview with Eric about

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